Design Level. On design level an overview of the overall System Design of the Comfort Range Balancer is given. For some selected subsystem the integration and internal components are also modelled in detail. As a sample below, the detailed view on the integration and internal view of the Range Problem Solver is given. The behaviour of some subsystems will be worked out on design level using ModelicaML and Modelica, in order to be able to perform simulations and verifications on design level. Besides the software systems the HW is modelled in the PrEEvision tooling. Figure 2-22 Overall Design of Comfort Range Balancer with subsystems Figure 2-23: Embedded Range Problem Solver on Design Level Figure 2-24: Internal View of Range Problem Solver Figure 2-25: Hardware Design Architecture of Comfort Range Balancer
Design Level. Functional Design Architecture A step forward in the design of the case study have been done using the “Functional Design Architecture”, that in this specific case refine the preliminary design of the system adding further details in terms of functional decomposition, flow ports and provides implementation details of functional mapping on HW items through allocations. Figure 2-4: Propulsion - Design Function Types Figure 2-5: Propulsion - example of FDA realized in different development environment. Hardware Design Architecture The following Hardware Design Architecture shown in Error! Reference source not found.
Design Level. The design level architecture further details the analysis level design by taking the software and hardware resources into consideration. (See also D6.1.1 for an overview the related design concept). Functional Design Architecture Figure 2-44. Functional Design Architecture of the Regenerative Braking System in Papyrus. Figure 2-44 shows the FunctionalDesignArchitecture. This model is focusing on base braking and does not include energy regeneration functionality. Figure 2-45 shows the period times of the included functions. Figure 2-45. Period times of functions Figure 2-46 (close-up) and Figure 2-47 (overall) shows timing constraints for end-to-end response requirements of the brake functionality. Figure 2-47 also show synchronization requirements and a brake-down of the end-to-end timing budget. Figure 2-46. Functional Design Architecture with end-to-end timing Figure 2-47. Functional Design Architecture with end-to-end timing Hardware Design Architecture Figure 2-48 shows an initial HardwareDesignArchitecture. Figure 2-48: Hardware Design Architecture of the Braking System in Papyrus. Allocation Figure 2-49: Function-to-node Allocation in the Braking System in Papyrus. Allocation on design level is represented in Figure 2-49, where function prototypes of the FunctionalDesignArchitecture are allocated to nodes in the HardwareDesignArchitecture.
Design Level. Functional Design Architecture The following Functional Design Architecture describes one realization of the features explained in chapter 2.1.1 Both features are implemented on the EVC. Please refer to the comment fields within Figure 2-2 for further details of each function.
Design Level. The design level architecture further details the analysis level design by taking the software and hardware resources into consideration. (See also D6.1.1 for an overview the related design concept). Functional Design Architecture Figure 2-30 shows the FunctionalDesignArchitecture. This model is focusing on base braking and does not include energy regeneration functionality.
Design Level. Functional Design Architecture The following Functional Design Architecture describes one realization of the features explained in chapter 2.1.1 Both features are implemented on the EVC. Please refer to the comment fields within Figure 3 for further details of each function. Figure 3: Functional Design Architecture of the EV Demo Hardware Design Architecture The following Hardware Design Architecture shown in Figure 4 describes the hardware realization for the features explained in chapter Error! Reference source not found.. For all parts only the connectors relevant for this model are shown. The battery system, delivers the energy which is guided though the High voltage junction box to the power electronic. The power electronic transforms the DC voltage to be provided to the EV motor. The electric vehicle controller is the main controller for many powertrain functions of an electric vehicle. All functions of this model run at this controller. The sensors in this model are needed for the selection of the driving mode. Figure 4: Hardware Design Architecture of the EV Demo
Design Level. On design level an overview of the overall System Design of the Comfort Range Balancer is given. For some selected subsystem the integration and internal components are also modeled in detail. As a sample below, the detailed view on the integration and internal view of the Range Problem Solver is given. The behavior of some subsystems will be worked out on design level using ModelicaML and Modelica, in order to be able to perform simulations and verifications on design level. Besides the software systems the HW is modeled in the Preevision tooling.
Design Level. The design level architecture further details the analysis level design by taking the software and hardware resources into consideration. (See also D6.1.1 for an overview the related design concept). Currently, the documentation correspond to a single wheel brake by wire model. Work is under way to extend to a full four-wheel model. Functional Design Architecture Figure 19 shows the FunctionalDesignArchitecture. The model is preliminary, as there is only one wheel and the full details of sensors and actuators are not represented.
