Description of the conceptual architecture Sample Clauses

Description of the conceptual architecture. This deliverable describes the conceptual architecture of use case T10.1 “Drives and Electric Motors in Industrial Applications”. The runtime certificate approach was implemented in the context of this use case. The experience produced knowledge that served as input to further develop the approach.
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Description of the conceptual architecture. Figure 4 shows the control electronic concept of the demonstrator. Soc PWM LCP Analog PWM + ADC FPGA UART MOC SPI AOC Figure 5 - Control electronic concept of the UC1 demonstrator The conceptual architecture of the first VSD prototype supports real-time performance characteristics using a single multi-core chip (MCU and FPGA). Figure 6 - Layered software architecture Software Architecture is divided into layers based on the N-tier architecture (see Figure 5). This strategy has been chosen because it isolates various system responsibilities from one another, so that it improves system portability, development and maintenance. On top of middleware API we have identified: • User interface – graphical UI and interfaces to intelligent UIs • External parameters – mapping internal parameters to external views • Parameter data base – handling the parameter value sharing across nodes • Application specific components – providing application functionality • Application framework – handling application to application co-ordination • Motor control – providing interface to motor control cores In the middleware layer we have: • Middleware component layer- implementing configuration, communication, scheduling • Middleware services layer – services like alarm handling, logging • High level protocols – for different fieldbuses • Routing – node to node routing Hardware close layer contains: • Real time operating system – operating system and related services • Clock synchronization – real time clock • Media access layer The architecture is based on components with well-defined interfaces. Components communicate using a blackboard. The schedulers provide event-driven and time-triggered execution environments. • In the time triggered execution environment computations are periodic. There can be more than one execution queue running at different frequency. Scheduling within the queue is co-operative. Scheduling between queues in pre-emptive. Control flow is done through ordering of computations. • In the event driven execution environment components are tasks. Computations are started by events (inputs, timers). Since scheduling is pre-emptive it is necessary to protect shared resources. The different nature of these execution environments means that components as a rule cannot be without modifications moved between these environments. The integration of Safe Torque Off is relatively straight forward (see Figure 6) as it is possible to bypass the software layers to reach SIL3,...
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Description of the conceptual architecture. A set of the specific requirements defined at D10.1 have guided the development in this task. Although the complete list of requirements is available in [REQ-T10_4] (from D10.2), next it will be described those that have already been taken into account for the conceptual architecture applied to the prototype. Requirement 15Q-WP10-REQ005 defines response time constraints that the system engineer should meet without excessively incrementing other costs. Intensive work on algorithm parallelization for the 3D object reconstruction has been carried out in order to achieve a version of the software able to take advantage from a multicore execution platform. Original sequential code was unable to run on several cores, thus preventing an optimal utilization of the proposed EMC2 execution platforms. This milestone has been achieved by speeding up some stages of the 3D reconstruction algorithm through the possibility to execute in parallel its corresponding code. Different features from OpenMP library have been extensively applied to the algorithm, like pragma directives for loops, thread pools and message queues which enabled us to improve performance by exploiting coarse parallelism on the inspection system prototype. This parallelization effort of the 3D reconstruction process using OpenMP has resulted in a parallel version which has been compared against the sequential one. Both versions have been modeled with the “art2kitekt” tool imported from WP2. This model has also allow us to analyze the performance critical 3D reconstruction process for a given execution platform. As a result, it has been obtained a response time improvement by OpenMP parallelization, around half time reduction with parallelism. This is a good result but smaller than expected mainly due to lack of CPU and cache affinity control provided by this approach. Furthermore, OpenMP framework does not provide a fine control of thread-to-core assignment. Then, an engineering process of design and analysis guided by the tool “art2kitekt” has been performed, resulting in a model of the parallel process aimed to reconstruct a 3D object. This model will allow us to optimize and fine-tune the parallelization model to take into account CPU hierarchies present in the selected execution platform.
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