Characterization Methodology Sample Clauses

Characterization Methodology. The xpipesLite switch was used as the basic building block to construct the 64-end nodes topologies under test. However, exploring the design space of topologies with such a large number of cores by means of their actual physical synthesis proved impractical due to synthesis time and memory capacity requirements. Therefore, this section presents a way to cut down on the number of physical synthesis tests while still characterizing quality metrics of the full topology with high accuracy. As already reported, the performance bottleneck of a topology lies in its longest switch-to- switch communication channel. Aware of this, for each topology under investigation, a subsystem composed of two communicating switches at the maximum possible distance in the topology is built, thus capturing the largest link delay in that topology. Logic synthesis for maximum performance and place and route are then performed to capture the real minimized switch-to-switch delay. Such delay (which is the critical path delay of the network too) is then used as the target delay to resynthesize, place and route all the possible switch-to-switch system combinations at all the possible link distances in the topology under test. The reason for this is that the goal is to accurately capture the switch cell area at a certain distance and at a certain target speed. It is well known from logic synthesis theory that as the target speed is decreased, a large area can be saved. In this direction, it would make no sense to synthesize switches for maximum performance when a long link limits overall network speed (unless decoupling techniques like link pipelining are used, as we will see later on). With this methodology, only a few selected synthesis runs for each topology need to be per- formed to characterize its delay and area as a whole. The approximation lies in the availability of enough routing channel space for regular routing of NoC links and in the accuracy of wire delays for links that undergo bending in the actual layout. Moreover, with this method it is also possible to capture the link buffering cost, in fact, by leveraging the report of the utilized physical synthesis tool, the inferred buffers along switch-to- switch links can be traced. In order to be as accurate as possible, two communicating ports of both switches in the test subsystem are left unconnected. They are the ports connecting to the network interfaces of processing cores, which are typically placed close to their switc...