Timing Closure Sample Clauses

Timing Closure. Since the final goal is high performance, the objective is to materialize, after topology place-and- route, the maximum speed achievable by the slowest NoC module (characterized in isolation with postlayout timing analysis). In the assumed architecture, the critical module turns out to be always the switch with the highest radix in the topology. The resulting speed upper bound, which ignores the effect of interswitch links, is reported in the first two rows in Table 5. For the slowest switch of each topology in isolation, the gap between postsynthesis and post-P&R speed ranges between 12% to 21%. The 2-ary 2-mesh exhibits a higher postsynthesis value due to the larger radix and a more severe post-P&R degradation due to the larger switch area compared with nonconcentrated topologies. When considering timing closure for the entire topologies, the degradation associated with interswitch link routing and with their synthesis techniques becomes apparent. Let us consider repeaterless links first (Table 5, third row). While 2-D mesh and 4-hypercube had the same performance upper-bound (since they have switches with the same maximum radix), the more challenging routing of the 4-hypercube gave rise to a 39% degradation of the critical path, while routing of the 2-D mesh turns out to be less critical. The 2-ary 2-mesh has some links longer than 4 mm, therefore interswitch routing has an even more relevant impact. This also hides the effect of Topology 4-ary 2-mesh 2-ary 4-mesh 2-ary 2-mesh Postsynthesis (WC Switch)) 1 ns 1 ns 1.15 ns Post-P&R (WC Switch) 1.12 ns 1.12 ns 1.4 ns Post-P&R repeaterless (Topology) 1.27 ns 1.56 ns 1.67 ns Post-P&R with repeaters (Topology) 1.19 ns 1.56 ns 1.5 ns Post-P&R with pipeline stages (Topology) – 1.19 ns 1.42 ns Table 5: Timing results. the higher switch radix, which is not the ultimate responsibility for the slower operating frequency. For all topologies, the critical path goes through the network links. Although postlayout effects of interswitch wires paint a dismal picture of topologies using long wires (because of the use of more dimensions or of the switch separation in the layout), designers can optimize wires to overcome these large delays. Activating repeater-insertion during topology synthesis enables the speedups illustrated by the fourth row of Table 5, denoting the best critical delay at which timing closure was achieved. Results are quite heterogeneous. The 2-D mesh further benefits from repeaters and achieves a 6% sp...