Optional Optical LC Connector Position Sample Clauses

Optional Optical LC Connector Position for Telecom Applications 28 5.7 Electrical Connectors 29 5.8 Pin Assignment 29 5.9 CFP4 Bail Latch Color Coding and Labeling 33 6 REGULATORY COMPLIANCE 34

Optional Optical LC Connector Position for Telecom Applications 28 5.7 ELECTRICAL CONNECTORS 29 5.8 PIN ASSIGNMENT 29 5.9 CFP4 BAIL LATCH COLOR CODING AND LABELING 33 6 REGULATORY COMPLIANCE 34 REVISION HISTORY Draft Date Revised Items 0.1 3/2/2014 Initial draft, based on CFP4 Baseline Design, Revision P 0.2 6/28/2014 2nd draft, based on revised CFP4 Baseline Design, Revision R. Some editorial errors were corrected in Rev.R Added description on Pin-out definition.

Optional Optical LC Connector Position for Telecom Applications 28 5.7 ELECTRICAL CONNECTORS 29 5.8 PIN ASSIGNMENT 29 5.9 CFP4 BAIL LATCH COLOR CODING AND LABELING 33 6 REGULATORY COMPLIANCE 34 REVISION HISTORY Draft Date Revised Items 0.1 3/2/2014 Initial draft, based on CFP4 Baseline Design, Revision P TABLE LIST Table 1-1: Control Pins 9 Table 1-2: Hardware Alarm Pins 11 Table 1-3: Management Interface Pins (MDIO) 12 Table 4-1: Voltage Power Supply 16 Table 4-2: Optional Reference Clock Characteristics 19 Table 4-3: Optional Monitor Clock Characteristics 20 Table 4-4: CFP4 Module Clocking Signals 20 Table 5-1: CFP4 Mechanical Characteristics 26 Table 5-2: CFP4 Module Insertion, Extraction Forces 26 Table 5-3: Optical Connectors 28 Table 5-4: CFP4 Host Connector Assembly 29 Table 5-5: CFP4 4x25Gbpt/s Pin Map 31 Table 5-6: CFP4 Bottom Row Piin Description for 4x25 Gbit/s Applications 32 Table 5-7: CFP4 Bail Latch Color Coding 33 FIGURE LIST Figure 1-1: CFP4 Functional Block Diagram 8 Figure 2-1: Reference +3.3V LVCMOS Output Termination 12 Figure 2-2: Reference 3.3V LVCMOS Input Termination 13 Figure 2-3: Reference MDIO Interface Termination 14 Figure 4-1: High Speed I/O for Data and Clocks 17 Figure 4-2: CFP4 Module Optional Loopback Orientation 18 Figure 4-3: Example of Clocking for 4 x 25 Gbit/s CFP4 Applications 21 Figure 4-4: Example of Clocking for 4 x 10 Gbit/s CFP4 Applications 21 Figure 5-1: CFP4 Module & CFP4 Module Mated in Host Quad Port System 22 Figure 5-2: Host Cage System and Mounting Method Overview 22 Figure 5-3: CFP4 Module Plug Connector Assembly 23 Figure 5-4: CFP4 Quad Port Host Connector Cover Assembly 23 Figure 5-5: CFP4 Host Connector Assembly 24 Figure 5-6: CFP4 Pin Map Connector Engagement 24 Figure 5-7: CFP4 Module Dimension Overview 25 Figure 5-8: Riding Heat Sink 27 Figure 5-9: Host Cage Top Surface Opening 27 Figure 5-10: CFP4 Connector Pin Map Orientation 30 Figure 5-11: CFP4 Module Label Recess 33 REFERENCE DOCUMENTS [1] CFP MSA Hardware Specification, Revision 1.4, June 7, 2010. [2] CFP MSA CFP2 Hardware Specification, Revision 1.0, July 31, 2013. [3] CFP MSA Management Interface Specification, Version 2.2, July 01, 2013. [4] IEEE P802.3bm, 40Gbit/s and 100Gbit/s Operation Over Fiber Optic Cables Task Force, xxxx://xxx.xxxx000.xxx/3/bm/index.html [5] IEEE Std 802.3TM-2012, Annexes 83A, 83B, and 86A. [6] IEEE Std 802.3TM-2012, Cl. 45, Management Data Input/Output (MDIO) Interface. [7] ITU-T Recommendation G.709 (2012) Interfaces for the Optical Transport Networ...

Optional Optical LC Connector Position for Telecom Applications 48 5.7 ELECTRICAL CONNECTORS 49 5.8 PIN ASSIGNMENT 49 5.9 CFP2 BAIL LATCH COLOR CODING AND LABELING 57 6 REGULATORY COMPLIANCE 64 REVISION HISTORY Draft Date Revised Items 0.0 Nov. 30, 2012 Initial draft, based on CFP2 Baseline Design, Release 1 0.1 Dec. 14, 2012 Edits from CFP MSA System OEM Reviewers comments - 0.2 Mar. 14, 2013 Added Table 2-5: Timing Parameters for CFP Hardware Signal Pins. Add Power Class 5 & 6 in Table 4-1 Voltage power supply Added future high speed electrical interface in Section 4.4. Changed Figure 4-1 to include common mode impedance termination. Changed REFCLK alternatives in Table 4-4 to be in line with what are specified in the MDIO specification. 0.3 Apr. 25, 2013 Added Figure 2-1 and Figure 2-2 Modified Figure 5-7, Figure 5-8 and Figure 5-10 according to the latest published CFP2 baseline drawing Added maximum weight value in Table 5-1 Replaced TBD with actual values in Table 5-2

Optional Optical LC Connector Position for Telecom Applications 28 5.7 ELECTRICAL CONNECTORS 28 5.8 PIN ASSIGNMENT 28 5.9 CFP2 BAIL LATCH COLOR CODING AND LABELING 30 6 REGULATORY COMPLIANCE 34 REVISION HISTORY Draft Date Revised Items 0.0 Nov. 30, 2012 Initial draft, based on CFP2 Baseline Design, Release 1 0.1 Dec. 14, 2012 Edits from CFP MSA System OEM Reviewers comments - 0.2 Mar. 14, 2013 Added Table 2-5: Timing Parameters for CFP Hardware Signal Pins. Add Power Class 5 & 6 in Table 4-1 Voltage power supply Added future high speed electrical interface in Section 4.4. Changed Figure 4-1 to include common mode impedance termination. Changed REFCLK alternatives in Table 4-4 to be in line with what are specified in the MDIO specification.

Optional Optical LC Connector Position for Telecom Applications 41 5.7 Electrical Connectors 42 5.8 Pin Assignment 43 6 PIN MAP FOR MULTI-PORT 40GBIT/S INTERFACES 47 7 REGULATORY COMPLIANCE 49 7.1 Laser Safety 49 7.2 ESD/EMI/EMC 49 7.3 Environment 49 8 APPENDIX I: THERMAL DESIGN EXAMPLE 50 8.1 Scope 50 8.2 Riding heat sink system 50 8.3 Assumption for thermal characterization and simulation 51 8.4 Preliminary Example Results 53 REVISION HISTORY Draft Date Revised Items

Optional Optical LC Connector Position for Telecom Applications 41 5.7 ELECTRICAL CONNECTORS 42 5.8 PIN ASSIGNMENT 43 6 PIN MAP FOR MULTI-PORT 40GBIT/S INTERFACES 47 7 REGULATORY COMPLIANCE 49 7.1 LASER SAFETY 49 7.2 ESD/EMI/EMC 49 7.3 ENVIRONMENT 49 8 APPENDIX I: THERMAL DESIGN EXAMPLE 50 8.1 SCOPE 50 8.2 RIDING HEAT SINK SYSTEM 50 8.3 ASSUMPTION FOR THERMAL CHARACTERIZATION AND SIMULATION 51 8.4 PRELIMINARY EXAMPLE RESULTS 53 REVISION HISTORY Draft Date Revised Items