Design Flow. If the Shared Sewer's Total Peak Design Flow, the Using Party's Peak Design Flow, or both, change along the length of the Shared Sewer, the Using Party's cost share must be calculated separately for each such segment. All Shared Sewers are eligible for reimbursement, including 8-inch diameter sewers. If the actual constructed sewer capacity exceeds its Total Peak Design Flow, due to topographic or other physical constraints, each Using Party's cost share must be based on its percentage of the Total Peak Design Flow, not the actual capacity.
Design Flow. All conveyance systems shall be designed to convey runoff from the 25-year storm unless otherwise approved or requested by the City. A backwater analysis is required for a proposed or existing pipe system to confirm the ability of the pipe system to convey the peak rate of runoff from the 25-year design storm event under tail water conditions anywhere in the pipe system. Structures such as catch basins (except as part of parking lot detention) and manholes for proposed pipe systems must provide a minimum of 0.5 feet of free board between the headwater surface (hydraulic grade line) and the top of the structure for flow from a 25-year storm.
Design Flow. Currently low power design in practise means: low voltage, small feature size, clock gating, operand isolation, and power management. Clearly low voltage is a key influence on power reduction due to its quadratic impact on the power dissipation. However, there are limits due to reduced performance and increased leakage current. Further small feature size reduces the switched capacitance and hence significantly reduces power. Usually these parameters are not at the distinction of the designer and their positive effect are assumed in the power dissipation predictions of the roadmaps anyway. Other means at the gate and circuit level provide only power reductions in the area of some 10-20%. Application specification Software Path Hardware Path Software Estimator Source Code Transformations Algorithmic Transformations Algorithm Estimator Compilation Behavioral Synthesis RTL Trans- formations RTL Estimator Memory and Datapath Mapping Control Synthesis Gate-Level Estimator Figure 1: Proposed Design Flow for Power Estimation and Optimisation SoC Architecture (Core Processors, Memories, Buses, Datapath, Control) Application Analysis (Timing, Power, Area) and Partitioning Control Synthesis SoC Architecture (Core Processors, Memories, Buses, Datapath, Control) SoC Architecture (Core Processors, Memories, Buses, Datapath, Control) Memory and Datapath Mapping Gate-Level Estimator Hardware Path Software Path RTL Estimator RTL Trans- formations Compilation Behavioral Synthesis Algorithm Estimator Algorithmic Transformations Source Code Transformations Software Estimator Power estimation and optimisation at the system level, during software design and system architecture definition, have been addressed by prior research work. However, no seamless design flow approach through these levels - considering the main power drains - has been developed and applied so far. Within POET this flow will be defined driven by concrete product developments by the user partners XXXX and ARM. The flow will be coupled to industry standard commercial tools as far as available, and missing links in the tool chain will be developed by the research partners of the project (OFFIS, CEFRIEL and POLITO) and commercially made available by the EDA partner OSC. For proper power analysis and optimisation, a full characterisation of the system components is needed. In order to minimise the time-consuming characterisation procedure, the number of libraries and technology files will be kept at a minimum....
