Monitored A/D Values Sample Clauses

Monitored A/D Values. ‌ Supported measurements are calibrated to stated accuracies over vendor specified operating temperature and voltage and should be interpreted according to previous sections. Table 28 Table 6. Monitored A/D Value Memory Map Address MDIORegisters Size Name Description Note 96-97 A060-A061 2 Transceiver Temp MSB at low address 1 98-99 A062-A063 2 Reserved 100-101 A064-A065 2 Laser Bias Current MSB at low address 1 102-103 A066-A067 2 Laser Output Power MSB at low address 1 104-105 A068-A069 2 Receive Optical Power MSB at low address 1 106-109 A06A-A06D 4 Reserved 192-193 A0C0-A0C1 2 Lane 0 Transceiver Temp MSB at low address 2 194-195 A0C2-A0C3 2 Reserved 196-197 A0C4-A0C5 2 Lane 0 Laser Bias Current MSB at low address 2 198-199 A0C6-A0C7 2 Lane 0 Laser Output Power MSB at low address 2 200-201 A0C8-A0C9 2 Lane 0 Receive Optical Power MSB at low address 2 202-207 A0CA-A0CF 6 Reserved 208-209 A0D0-A0D1 2 Lane 1 Transceiver Temp MSB at low address 2 210-211 A0D2-A0D3 2 Reserved 212-213 A0D4-A0D5 2 Lane 1 Laser Bias Current MSB at low address 2 214-215 A0D6-A0D7 2 Lane 1 Laser Output Power MSB at low address 2 216-217 A0D8-A0D9 2 Lane 1 Receive Optical Power MSB at low address 2 218-223 A0DA-A0DF 6 Reserved 224-225 A0E0-A0E1 2 Lane 2 Transceiver Temp MSB at low address 2 226-227 A0E2-A0E3 2 Reserved 228-229 A0E4-A0E5 2 Lane 2 Laser Bias Current MSB at low address 2 230-231 A0E6-A0E7 2 Lane 2 Laser Output Power MSB at low address 2 232-233 A0E8-A0E9 2 Lane 2 Receive Optical Power MSB at low address 2 234-239 A0EA-A0EF 6 Reserved 240-241 A0F0-A0F1 0 Xxxx 3 Transceiver Temp MSB at low address 2 242-241 A0F2-A0F3 2 Reserved 244-245 A0F4-A0F5 0 Xxxx 3 Laser Bias Current MSB at low address 2 246-247 A0F6-A0F7 2 Lane 3 Laser Output Power MSB at low address 2 248-249 A0F8-A0F9 2 Lane 3 Receive Optical Power MSB at low address 2 250-255 A0FA-A0FF 6 Reserved For WDM Implementation:
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