DMA Controller with Integrated Network Interface Clause Samples

DMA Controller with Integrated Network Interface. The DMA controller incorporates standard techniques (also used in ARM’s A15) to support single remote read/write DMA operations by accessing data from device memory through standard AMBA AXI read/write operations. Each DMA controller is also attached to a custom network interface (NI) that provides access to the NoC. The NI is responsible for packetization (or de-packetization) of data to/from network packets directed to/from memory, as well as size conversions; frequency conversions are currently not needed in our current VP, since our single port memory uses an asynchronous event-based interface. Other NI characteristics related to fault tolerance, security and power-efficiency can also be specified in the future. The implemented DMA controller uses a flit-by-flit fetch and deposit scheme with small buffers to store data before transmitting to the network via the attached network interface. Recently proposed fly-by schemes are also interesting: they are faster due to direct transmission of data from the device to the NoC but have a synchronization overhead since an array of semaphores is required. Atomic DMA transactions and direct memory-to-memory copy (so called distributed DMAs) are also interesting. For DMA operations, configuration and control information is transferred through the system bus and includes source address (SRC - 40 bits), destination address (DST - 40 bits) and length in bytes (DST - 16 bits). This information is processed and encapsulated within the NoC packet.
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