NVIDIA Tegra X2 definition

NVIDIA Tegra X2. The Tegra X2 is a mobile integrated graphics solution by NVIDIA. It is built in a 16 nm process, and based on the GP10B graphics processor. The device features 256 shading units, 16 texture mapping units and 16 Raster Operations (ROP) accelerators. The GPU is operating at a frequency of 854 MHz, which can be boosted up to 1465 MHz [29]. It draws up to 15 Watt. Figure 9 shows the structure of NVIDIA Tegra Pascal GPU. The main features of NVIDIA Tegra X2 are: CPU: NVIDIA Denver2 ARMv8 (64-bit) dual-core + ARMv8 ARM Cortex-A57 quad-core (64-bit), clock up to 1465 MHz Figure 9: NVIDIA Tegra GPU Altera Stratix 10 SoC: Altera Stratix 10 SoCs are manufactured with Intel 14 nm FinFET process technology. They feature the new HyperFlex core architecture. It uses 64 bit quad- core ARM Cortex-A53 Hard Processor System (HPS) as shown in Figure 10 [17]. The main features of Stratix 10 SoCs are: • Quad-core 64-bit (ARMv8) ARM Cortex-A53 operating at up to 1.5 GHz HPS Vector floating-point unit single and double precision, ARM Neon media processing engine for each processor Over 2.3 Tbps bandwidth for parallel memory interfaces with support for DDR4 SDRAM at 2,666 Mbps Intel SoC FPGA Embedded Development Suite (EDS) featuring the ARM Development Studio 5 Figure 10: Structure of Altera Stratix 10 SoC Board support packages for popular operating system including Linux, VxWorks, uC/OS- II and uC/OS-III, etc. Xilinx Zynq MPSoC Ultrascale+: The newest Zynq product family, the Multi-Processor Sys- tem on Chip (MPSoC) Ultrascale+ supports many different interfaces – some of which can be used both externally and internally. The UltraScale+ enables dual-voltage operation, enabling to choose either the highest absolute performance or the highest performance-per-watt [53]. The MPSoC has all modern power saving capabilities (supports DVFS as well as dynam- ically switching off unused I/Os and components). For power management, there are four independently controllable power domains: the Programmable Logic (PL) plus three within the Processing System (PS) (full power, lower power, and battery power domains). Figure 11 shows the structure of UltraScale+ MPSoC. The components of the MPSoC are interconnected and connected to the FinFET+ Programmable Logic (PL) through a multi- layered ARM AMBA AXI non-blocking interconnection that supports multiple, simultaneous master-slave transactions. Traffic through the interconnection can be regulated by the quality of service (QoS) block. Twelve d...
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Examples of NVIDIA Tegra X2 in a sentence

  • NVIDIA Tegra X2, Altera Stratix 10 (400), and the Xilinx Zynq Ultra- Scale+ have turned out in this way to be the best suitable hardware platforms for the TULIPP use cases and are analysed here in more detail.

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