Common use of Electrical Connectors Clause in Contracts

Electrical Connectors. ‌ CFP4 host electrical connector supplier information will be added to Table 5-4 in a future release of this MSA. Table 5-4: CFP4 Host Connector Assembly Part Number Supplier Part Name TBA TBA Cage TBA TBA Host Connector Cover Assembly TBA TBA Host Connector 5.8 Pin Assignment‌ The CFP4 connector has 56 pins which are arranged in Top and Bottom rows. The CFP4 connector supports the following configurations: Four (4) 25Gbit/s TX lanes plus four (4) 25Gbit/s RX lanes; The CFP4 pin-orderings are shown in Table 5-5. The CFP4 TOP pin-out definition uses the same pin-ordering convention as CFP and CFP2. There is also an optional CFP4 TOP ALT1 pin-out definition which follows the QSFP pin-ordering convention. All modules must support the baseline TOP pin-out definition. The optional TOP ALT1 pin-definition can be switched to after power-up by using MDIO commands to switch the pin-ordering. For details, please refer to “CFP MSA Management Interface Specification” Detailed description of the bottom row pins 1 through pin 28 are given in Table 5-6. Note the REFCLK pins are located on the top row along with the high-speed TX and RX data pins. A single-ended REFCLK is an option. The CFP4 connector pin map orientation is shown in Figure 5-10.

Electrical Connectors. ‌ CFP4 host electrical connector supplier information will be added to Table 5-4 in a future release of this MSA. Table 5-4: CFP4 Host Connector Assembly Part Number Supplier Part Name TBA TBA Cage TBA TBA Host Connector Cover Assembly TBA TBA Host Connector 5.8 Pin Assignment‌ The CFP4 connector has 56 pins which are arranged in Top and Bottom rows. The CFP4 connector supports the following configurations: Four (4) 25Gbit/s TX lanes plus four (4) 25Gbit/s RX lanes; The CFP4 pin-orderings are shown in Table 5-5. The CFP4 TOP pin-out definition uses the same pin-ordering convention as CFP and CFP2. There is also an optional CFP4 TOP ALT1 pin-out definition which follows the QSFP pin-ordering convention. All modules must support the baseline TOP pin-out definition. The optional TOP ALT1 pin-definition can be switched to after power-up by using MDIO commands to switch the pin-ordering. For details, please refer to “CFP MSA Management Interface Specification” Detailed description of the bottom row pins 1 through pin 28 are given in Table 5-6. Note the REFCLK pins are located on the top row along with the high-speed TX and RX data pins. A single-ended REFCLK is an option. The CFP4 connector pin map orientation is shown in Figure 5-10.