Assertions Clause Samples

Assertions. This technique is used with both static and dynamic verification. An assertion is a statement regarding some expected behaviour of the design. Assertions behave as checks and can be embedded into the design early, i.e., at the design time. They can also be inserted later by verification engineers. They are used to verify assumptions about how a design should operate. Assertions are very appropriate for verifying protocol scenarios at interfaces. They are also used to express definitive properties about a system or module. Besides enabling DFV as previously discussed, assertions can be perceived as providers of internal test points in the design, therefore increasing the observability and ability to debug it. Instead of comparing the system as a whole to a complex model, smaller monitors are put in place, therefore making strategically placed checks on important parts of the design. Additionally, assertions can increase the verification productivity and minimize the integration effort.