Target Applications Clause Samples

Target Applications. The ASIC department of the Switching & Routing systems division of ASEL is working in the area of very advanced, high complexity ASICs on a large variety of telecommunication areas. This includes not only ASIC designs for ISDN and ATM switching products or cross-connect transmission systems, but also ASICs for access systems that are located at the central office or in customer premises equipment. In addition, the ASIC department has built up core competence knowledge in the area of embedded systems design and provides a configurable embedded processor platform to other ASIC design centres in terms of an intellectual property. This includes not only the VHDL and embedded software code, but also the provision of a methodology for using the processor platform within other designs, i.e. a compilation, synthesis, co-simulation, verification and test strategy. ASEL is in charge of extending its processor platform methodology to cover also low power design issues and tools, as low power is and becomes a crucial matter for ASIC designs throughout ASEL. ▇▇▇▇ especially sees the need for power estimation and optimisation tools that can be used very early in the design phase and that covers also the proportion of the power that is consumed by the software running on the embedded processor. Since modelling and simulation of complex ASIC with C/C++ models becomes more and more important and is already code of practise at many design centres of ASEL, power estimation and optimisation at this level is a key issue for making early trade-offs and an optimal HW/SW partitioning. As low power is a critical issue for all current and especially future designs, ASEL intends to drive the development and exploitation of tools in that area to make sure that actual and future requirements will be met. The developed tools and methodologies will be used in power critical projects to overcome the lack of commercial solutions. Furthermore ASEL will be able to spread the methodologies to other design centres via his processor platform. ARM will apply the POET tools and methodology to the design characterisation of SoC designs which include an on-chip cache-based processor (as is typically found in most such designs). The implementation of the cache architecture and operation can have a substantial impact on the overall system power consumption – cache size and depth and hit/miss rates, write-buffering type and fetch block size, and cache-flushing decisions all impact the overall system ...