Production Testing. Operations for the controlled flow of Hydrocarbons to the surface for the purpose of measuring flow rates or flowing pressures, or gaining other subsurface data.
Production Testing full rollout;
Production Testing. Control the production process within the operational tolerances listed in Tables 5A and 5B. Provide access to the mixing unit discharge stream for sampling purposes. Suspend production when the Engineer’s test results exceed the operational tolerances. The Engineer will allow production to resume when test results or other information indicate the next mixture produced will be within the operational tolerances listed in Tables 5A and 5B. Take corrective action to address deficiencies. Table 5A Operational Tolerances Property Test Method Requirements Asphalt content, % by wt. Tex-236-F1 or asphalt meter readings Design target ±0.5
Production Testing. The Contractor and Engineer must perform production tests in accordance with Table 16. The Contractor has the option to verify the Engineer’s test results on split samples provided by the Engineer. Determine compliance with operational tolerances listed in Table 11 for all sublots. Take immediate corrective action if the Engineer’s laboratory-molded density on any sublot is less than 95.0% or greater than 97.0% to bring the mixture within these tolerances. The Engineer may suspend operations if the Contractor’s corrective actions do not produce acceptable results. The Engineer will allow production to resume when the proposed corrective action is likely to yield acceptable results. The Engineer may allow alternate methods for determining the asphalt binder content and aggregate gradation if the aggregate mineralogy is such that Tex-236-F, Part I does not yield reliable results. Provide evidence that results from Tex-236-F, Part I are not reliable before requesting permission to use an alternate method unless otherwise directed. Use the applicable test procedure as directed if an alternate test method is allowed. Table 16
Production Testing. Once the SOC accelerator has been manufactured, these prototypes must then undergo testing to ensure the IP developed on the Altera development platform is successfully ported to the new hardware. The different hardware features of this board must be tested to ensure no unforeseen problems have arisen during the manufacturing process.
Production Testing. The hardware was first tested in a static condition, i.e. all power supplies are tested to fall within design tolerances at no-load and full-load. The Built-in-self-test is run selecting high dynamic load conditions for dynamic testing. Typically, this is a combination of memories tested using F-0-F patterns and high frequency processor switching with the FPGA. The FPGA design has variable current load modules (known as burners) that can be enabled and disabled to alter the dynamic load in the FPGA. This simulates different levels of customer usage. During such testing, all power supplies are monitored using an Oscilloscope with low frequency filtering enabled to ensure no noise or voltage excursions beyond nominal limits are observed. Also, all power supplies are observed using AC coupling to check high frequency stability. During BIST, power supplies are monitored to ensure they are within specification at all times during testing. Additionally, power supplies are margined up and down to ensure they are correctly monitored by the on-board UCD9090 device. This is done repeatedly during testing to ensure stability. The following tests are repeated throughout the production test period (typically 3½ hours). Test Onboard Setting PSU Voltage Onboard Power Load Margin Low Step through variable current loads (8 steps minimum current to maximum) Nominal 2 Nominal 3 Margin High Margin High Margin Low Minimum Step through variable current loads (8 steps minimum current to maximum) Minimum Step through variable current loads (8 steps minimum current to maximum) Minimum Table 1: list of repetitive tests These measurements are recorded as part of normal BIST testing.
Production Testing. During design the Flash interface was extensively tested through a combination of software and firmware, verifying programming, erasure and verification functionality. After manufacture, the Flash memory is programmed with a default program and used within the production environment to program the FPGA, thus proving it is functional and connected.
Production Testing. Memories were tested using a variety of access patterns and data patterns to fully characterize the interfaces. In all cases, the tests were run at nominal frequency (2133 MTPS/1066MHz) and at a higher frequency (2400 MTPS/1200MHz). Memory tests were run with power supplies margined high, nominal and low. The patterns used for testing are shown below. Pattern Description Typical Use Sequence A monotonically rising sequence of numbers e.g. 0 1 2 3 Pseudo-Random sequence of 32 Used for basic debug. Allows easy identification of repeated numbers, address bit errors etc. Tests all possible sequences of 1s and 0s on all PRBS Rolling 1 Rolling 0 F-0-F 5-A-5 bit numbers. Sequence of values with a single set bit which moves from bit 0 to bit 31 before starting again at bit 0. Sequence of values with a single unset bit which moves from bit 0 to bit 31 before starting again at bit 0. Sequence of 0xffffffff followed by 0x00000000 repeated. Sequence of 0x55555555 followed by 0xaaaaaaaa repeated. lines in the minimum time. Useful for showing signal integrity and reflection issues. Finds interconnected data bits and can show crosstalk between bits more clearly than PRBS. Can also clearly show stuck low bits. Finds interconnected data bits and can show crosstalk between bits more clearly than PRBS. Can also clearly show stuck high bits. Very high switching currents and simultaneous switching. Maximal test for I/O power supplies. Like F-0-F but adjacent bits are always inverses thus dynamic power is lower. Can show weak crosstalk between lines, or some specific driver issues. Table 3: patterns used for testing
Production Testing. The production BIST runs using communications across the PCIe interface, and also checks that this interface has successfully trained to Gen 3, x8. The appropriate section of the BIST report is copied below. INFO - PCIe-385a BIST Firmware svn version number: 2350. INFO - PCIe-385a BIST NIOS version number: 2.34 INFO - Serial Number: SN7095150 INFO - Card revision: v0301 INFO - FPGA type: A10 INFO - FPGA fabric speed: 2 INFO - FPGA transceiver speed: 3 INFO - FPGA part number: 10AX115N3F40E2SG INFO - Prog time: 10:58, day: 10, month: 6, year: 16 INFO - MAC Address SFP+ 0: 00:0c:d7:00:27:a7 INFO - MAC Address SFP+ 1: 00:0c:d7:00:27:a8 INFO - Customer data: INFO - PCIe link status 0x1083. Gen 3, x8 Table 5: production testing result
Production Testing. During production, the QSFP28 cages are populated with QSFP-SR4-40G transceivers connected together using GMP-B-1-12-F-MM4-LS-MTP/PC-MTP/PC-1M fibre optic patch cord. This allows for full transmit and receive testing of the eight QSFP transceivers. The BIST sets up the FPGA transceivers and enables the channels. It then locks the receivers using test patterns. A single error is injected on each transmitter to ensure the loopback is complete and that errors can be detected. INFO - T000 - QSFP0 temperature 35 deg C INFO - T000 - QSFP0 reading error counts INFO - T000 - channel 0: bit count upper = 0xad, bit count lower = 0xc11f5140 INFO - T000 - channel 0: error count upper = 0x0, error count lower = 0x0 INFO - T000 - channel 1: bit count upper = 0xad, bit count lower = 0xd999dfc0 During the full BIST, the error status of all receivers is monitored. Any failure results in reject of the card. The lines related to QSFP testing are reproduced below. INFO - T000 - QSFP0: Checking for PLL lock INFO - T000 - QSFP1: Checking for PLL lock INFO - T000 - Starting word alignment INFO - T000 - QSFP0: Checking for word alignment INFO - T000 - QSFP1: Checking for word alignment INFO - T000 - Word alignment complete INFO - T000 - Starting PRBS checkers INFO - T000 - QSFP0: Checking error counts are zeroed INFO - T000 - channel 0: bit count upper = 0x17, bit count lower = 0xe1db4f80 INFO - T000 - channel 0: error count upper = 0x0, error count lower = 0x0 INFO - T000 - channel 1: bit count upper = 0x17, bit count lower = 0xfa66b740 INFO - T000 - channel 1: error count upper = 0x0, error count lower = 0x0 INFO - T000 - channel 2: bit count upper = 0x18, bit count lower = 0x12f1ec00 INFO - T000 - channel 2: error count upper = 0x0, error count lower = 0x0 INFO - T000 - channel 3: bit count upper = 0x18, bit count lower = 0x2b7d2280 INFO - T000 - channel 3: error count upper = 0x0, error count lower = 0x0 INFO - T000 - QSFP1: Checking error counts are zeroed INFO - T000 - channel 0: bit count upper = 0x18, bit count lower = 0x50484900 INFO - T000 - channel 0: error count upper = 0x0, error count lower = 0x0 INFO - T000 - channel 1: bit count upper = 0x18, bit count lower = 0x6eefa0c0 INFO - T000 - channel 1: error count upper = 0x0, error count lower = 0x0 INFO - T000 - channel 2: bit count upper = 0x18, bit count lower = 0x877ad4c0 INFO - T000 - channel 2: error count upper = 0x0, error count lower = 0x0 INFO - T000 - channel 3: bit count upper = 0x18, bit count lower = 0xa00...
