Baseboard ID. MEZZ_PRSNTA1_N in connector A and MEZZ_PRSNTB1_N in connector B is connected to ground for this case. Baseboard ID is an optional feature for special baseboard to identify itself to Mezzanine card. It is only implemented when Mezzanine card needs to have awareness of different baseboard types, and the baseboard Mezzanine card interface is not a single root port PCIe. Baseboard ID only applies connector A and Connector B. The implementation example of Baseboard ID circuit is shown in Figure 31. Baseboard P3V3_AUX R4 10K BMC GPIO(POR=Low) P3V3_AUX U3 MEZZ_PRSNTx2_N U4 MEZZ_PRSNTx1_N/ BASEBOARD_ID_x U5 0Ohm 1MOhm (To avoid floating, optional depending on Mezzanine card implementation) Note: x=A or B Mezzanine card identifies different of Baseboard based on the resistor pair R1/R2 shown in Table 16. Ω Ω KΩ Ω KΩ Ω KΩ Ω KΩ Ω KΩ Ω KΩ Ω Ω Ω KΩ Ω KΩ Ω KΩ Ω KΩ Ω KΩ Ω KΩ Ω Mezzanine card has a 4 seconds window to sample Baseboard ID signal, after both P12V_AUX and P3V3_AUX ready. BMC may disable baseboard ID output by GPIO after 4 seconds and change the multipurpose pin for Mezzanine card present purpose. Mezzanine card implementation shall consider the tolerance of P3V3_AUX, R1, and R2 when doing the sampling. P3V3_AUX has ±5% tolerance and R1, R2 has ±1% tolerance. R1 and R2 are selected to ensure a minimal of 240mV gap between 2 IDs, considering the tolerances above. Input current shall also be considered on Mezzanine card side to ensure correct reading of baseboard ID. 1MOhm pull low is optional at Mezzanine card side to avoid floating of input at Mezzanine card side “Baseboard ID Detection Circuit”. There are 2x typical implementations for Mezzanine card to implement Baseboard ID sampling. Mezzanine card vendors are not limited to these two implementations as long as the Mezzanine card is able to identify correct baseboard ID and initialized itself properly. • Using comparator to compare the voltage BASEBOARD_A/B_ID pins with reference voltage. It is preferred that the reference voltage is generated from P3V3_AUX and voltage divider. This helps to cancel out the ±5% tolerance on P3V3_AUX DC level. • Using ADC to identify voltage level on BASEBOARD_A/B_ID pins during 4 seconds window after both P12V_AUX and P3V3_AUX ready. P3V3_AUX is preferred to generate the voltage reference of ADC if it applies. 5 Management Interface There are two options of management interfaces on PCIe Mezzanine NIC for BMC’s out-of-band communication. Both interfaces should be routed from mezzanine card connector to NIC chipset. It is preferred that BMC firmware can choose to hand shake with either interfaces to have out-of-band channel. Only one interface need to be up and running for out-of-band traffic at a given time. The original OCP Mezzanine 1.0 specification only defines I2C side band interface to work with Facebook OCP Intel® motherboard V2.0. Starting Facebook OCP Intel® motherboard V3.0, the baseboard supports both I2C side band and NC-SI side band. NC-SI side band is the preferred interface due to higher speed and lower image transfer time for FW update from out-of-band. For new design, PCIe Mezzanine NIC has to implement NC-SI side band interface. It is preferred to implement I2C side band for compatibility with baseboard with I2C side band only. Management interface shall support both IPv4 and IPv6. 5.1 I2C side band 5.2 NC-SI side band 5.3 MAC address of management interface
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