Probe Testing definition

Probe Testing means testing, using a wafer test program as set forth in the applicable Specifications, of a wafer that has completed all processing steps deemed necessary to complete the creation of the desired NAND Flash Memory Integrated Circuits in the die on such wafer, the purpose of which test is to determine how many and which of the die meet the applicable criteria for such die set forth in the Specifications.
Probe Testing means testing, using a wafer test program as set forth in the applicable specifications, of a wafer that has completed all processing steps deemed necessary to complete the creation of the desired Stack DRAM integrated circuits in the die on such wafer, the purpose of which test is to determine how many and which of the die meet the applicable criteria for such die set forth in the specifications.
Probe Testing has the meaning set forth in the Manufacturing and Sale Agreement.

Examples of Probe Testing in a sentence

  • In addition, the Qualified Probed Wafer Demand Forecast will include the level of Probe Testing, marking specification and packaging requirements, requested delivery date and place of delivery for the Qualified Probed Wafers, which information will be updated by Intel on a weekly basis as necessary.

  • In addition, the Demand Forecast will include the level of Probe Testing, marking specification and packaging requirements, requested delivery date and place of delivery for the Probed Wafers, which information will be updated by Intel on a weekly basis as necessary.

  • The Joint Venture Company will designate the WIP (other than WIP for Unique Products of Micron) for Micron immediately prior to Probe Testing.

  • In addition, the Demand Forecast will include the level of Probe Testing, marking specification, requested delivery date and place of delivery for the Designated Technology Memory Wafers, which information will be updated by Intel on a weekly basis as necessary.

  • In addition, the Demand Forecast will include the level of Probe Testing, marking specification, requested delivery date and place of delivery for the Probed Wafers, which information will be updated by Intel on a weekly basis as necessary.

  • The Joint Venture Company will designate the WIP (other than WIP for Unique Products of Intel) for Intel immediately prior to Probe Testing.

  • The Purchaser and Inotera agree to work together in good faith to define mutually agreeable control and process mechanisms, including the following: (a) e-test (also known as parametric test capability); (b) qualification methodology plan; (c) product qualification support; (d) Probe Testing capability; (e) change control process; and (f) failure analysis capability and methodology.

  • When a Party converts Designated Technology Devices into Designated Technology Memory Wafers under this Agreement, such conversion shall be calculated using a conversion factor methodology to be agreed between the parties that takes into account the real-time die yield at Probe Testing, the back-end die yield and any other factor that the Parties agree.

  • In addition, the Demand Forecast will include the level of Probe Testing, marking specification, requested delivery date and place of delivery for the Probed Wafers, which information will be updated by Micron on a weekly basis as necessary.

  • If the Joint Venture Company does not elect to have WIP so designated, Micron will designate the WIP for specified customers after Probe Testing.


More Definitions of Probe Testing

Probe Testing shall have the meaning set forth in the Intel Singapore Supply Agreement.
Probe Testing means testing, using a wafer test program as set forth in the applicable Specifications, of a wafer that has completed all processing steps deemed necessary to complete the creation of the desired NAND Flash Memory Integrated Circuits in the die on such wafer, the purpose of which test is to determine how many and which of the die meet the applicable criteria for such die set forth in the Specifications. “Probed Wafer” means a Prime Wafer that, using either the [***] or [***] Process Technology Node, has been processed to the point of containing NAND Flash Memory Integrated Circuits organized in multiple semiconductor die (but before singulation of said die into individual semiconductor dice), that has undergone Probe Testing and any other mutually agreed upon special processing or handling.