IP Cores definition

IP Cores means Existing IP Cores and Developed IP Cores. “Existing IP Cores” means standard cell libraries delivered in the format of gate net list and GDS data, or in writing, and the categories of which are listed in Schedule A-1. “Developed IP Cores” means standard cell libraries delivered in the format of gate net list and GDS data, or in writing, which will be developed by REL for RSP under 55nm Development Agreement, and the categories of which are listed in Schedule A-2. “PDK” means Existing PDK and Developed PDK. “Existing PDK” means process design kits, such as design manual, design rule files, Spice model, WAT condition, to be delivered in source code, or in writing, and the categories of which are listed in Schedule B-1. “Developed PDK” means process design kits, such as design manual, design rule files, Spice model, WAT condition, to be delivered in source code, or in writing, which will be developed by REL for RSP under 55nm Development Agreement, and the categories of which are listed in Schedule B-2. “ESD Design Manual” means Existing ESD Design Manual and Developed ESD Design Manual. “Existing ESD Design Manual” means design manual documents for ESD (electrostatic discharge design), including ESD circuit design sample, which are listed in Schedule C. “Developed ESD Design Manual” means design manual documents for ESD, including ESD circuit design sample, which will be developed by REL for RSP under 55nm Development Agreement. “REL EDA Tools” means the EDA software tools and wrapper tools delivered in executable binary code, which are listed in Schedule D.
View Source
IP Cores means the Licensor’s IP cores as provided on the marketplace of Amazon Web Services.
View Source
IP Cores are hard cores and/or soft cores included in and/or provided with a FPGA or FPSC product, including the IP Cores listed on Appendices C and K.
View Source

Examples of IP Cores in a sentence

  • For the avoidance of doubt, Support Services are provided only with respect to the integration of the Licensed IP Cores into the Licensed Product as contemplated under Article 2 hereof.

  • Without limiting the preceding sentence, Support Services will not be provided with respect to (i) the Licensed IP Cores other than as described in the preceding sentence, (ii) any other product or service of SiFive, or (iii) any product or service of any third party.

  • Licensee (as defined below) wishes to license the Licensed Technology (as defined below) in order to develop integrated circuit devices that incorporate Sonics’ IP Cores (as defined below).

  • In the event Licensee sells Devices incorporating one or more different Sonics IP Cores (e.g., an SB IP Core and a Synapse 3220 IP Core), Licensee shall only have to pay a royalty equal to the highest royalty rate from any one (1) IP Core incorporated in such Devices.

  • Broadcom wishes to license the Licensed Technology in order to develop integrated circuit devices that incorporate Sonics IP Cores.

  • Xilinx expressly excludes from this warranty engineering samples (ES) of Hardware Product, any customized devices, such as Xilinx’s Hardwire™ and EasyPath™ devices, software, IP Cores and any services.

  • Your grant of license and use of the Silex Insight IP Cores under this End User License Agreement are limited to (beta) testing, evaluation purposes, and creating a proof of concept.

  • If you license any DesignWare Cores that are Hard IP Cores, you understand that you may be required to obtain appropriate licenses to technology libraries (such as standard cell and I/O libraries) from a supplier of such libraries for the applicable manufacturer, and that if this is case, you are responsible for getting these licenses at your own cost.

  • After finalisation of the first design based on the synthesizable HDL IP-Cores, Licensee shall deliver to Licensor’s Technical Officer a short summary report containing: the experience gained by using the licensed synthesizable HDL IP- Cores, their quality and usefulness, the adequacy and completeness of the designs provided by Licensor, the advantage of using the licensed synthesizable HDL IP-Cores and any proposal for improvements in the IP-Cores or their associated documentation.

  • Corrections as such are changes, aimed at rectifying a design error or “bug”, to the delivered source code, object code, libraries, and executable programs delivered as part of the SystemC IP- Cores or directly generated by them.