Static Verification Clause Samples

Static Verification. Static verification is a collection of techniques that do not rely on simulation. Formal verification is the static counterpart of simulation. Instead of applying carefully generated stimuli to a design like simulation does, formal verification tries to prove that the DUT operates correctly under all possible stimuli, therefore proving or disproving the correctness of a design. Static verification uses formal methods or mathematics for achieving that goal and therefore is complete by nature, given that the modelling was accurate and representative. For instance, if a property of a design is proved successfully, it will be valid for every input scenario and every possible state scenario. However, proving such statement can be a cumbersome task that might involve achieving partial proofs through an user-guided process. Static verification goes beyond proving the correctness of a design through property proving. There are examples where static verification techniques were and still are being used by the industry with a high degree of success. These are loosely termed formal apps. The most notable scenario is equivalence checking, typically done over different views of the same DUT, typically gate-level versus RTL [11]. Proving clock domain crossing solutions are appropriate is also a problem that can be solved with static verification [15] [16]. Other uses include power-aware formal verification, linting, and connectivity checks.