Speculation in Current Architectures Sample Clauses

Speculation in Current Architectures. While speculative behavior is generally left unspecified in current instruction-set architectures (ISAs), common archi- tectures do provide rudimentary barriers. The x86-64 ISA specifies that the lfence instruction prevents speculative out- of-order execution [16], and ▇▇▇ defines speculation barriers, e.g., the SSBB instruction [17]. Furthermore, ▇▇▇ proposes architectural extensions to allow software to entirely disable categories of speculation or to keep speculation in one context exclusively [18]. These speculation barriers and mechanisms have provided a crucial handle in ISA specifications that allow software mitigations for transient-execution attacks. However, the lack of general guarantees on speculative execution poses great risks, and will inevitably result in overly conservative hardware and software. Barriers in hardware must prevent all speculation, and these barriers will be used liberally by software to prevent esoteric potentialities, as the ISA provides no other guarantees on behavior in speculation. This conun- drum is similar to memory-consistency models, where lack of specification results in overuse of memory barriers [19]. Memory model specification may at first appear unneces- sary in an ISA, but has been proven to be necessary for portable concurrent algorithms. In the same way, portable, high-performance mitigations of transient-execution attacks require some guaranteed limits on speculation.
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