Receiver Data (and Clock. 29 The Receiver Data is defined in IEEE P802.3ba Annex 83A and Annex 83B defining CAUI and XLAUI. The 30 Figure 4-1: High Speed I/O shows the recommended termination for these circuits. Alternate signaling logic 31 are OTL3.4 and OTL4.10 which are specified in [11] ITU-T RECOMMENDATION G.709, Amendment 3. 32 Lane orientation and designation is specified in the pin-map tables Table 5-6, and Table 6-1. 1 Figure 4-1: High Speed I/O for Data and Clocks
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