ANNEX 1 RDA TECHNOLOGIES LIMITED CORTEX-A5 UP / CORTEX-A5MP / CORTEX-A5 FPU / CORTEX-A5 NEON

Exhibit 4.16

ANNEX 1

RDA TECHNOLOGIES LIMITED

CORTEX-A5 UP / CORTEX-A5MP / CORTEX-A5 FPU / CORTEX-A5 NEON

TLA Number		LEC-TLA-547
Legal Counsel		AF
Annex Effective Date		9 February 2012

This Annex 1, when signed by both parties, shall form part of and be incorporated into the Technology Licence Agreement (“TLA”) between the parties (document reference as identified in the table above). Solely for the purposes of interpretation of the TLA with respect to this Annex 1, to the extent that the provisions contained in this Annex 1 conflict with any of the provisions of the TLA the provisions contained in this Annex 1 shall prevail over and shall supersede the conflicting provisions in the TLA.

SECTION 1 — ARM TECHNOLOGY

SECTION 1.1 — CORTEX-A5 UP

PART A TECHNICAL REFERENCE DOCUMENTS

Section 1

Technical Reference Manuals

Part Number	Description	Disclosure Rights	Delivery Date
***	Technical Reference Manual - PDF	N	Within ten working days of Annex Effective Date
***	Technical Reference Manual - FrameMaker	D	Within ten working days of Annex Effective Date
***	Errata List	N	Within ten working days of Annex Effective Date
***	Supplementary Datasheet	N	Within ten working days of Annex Effective Date
***	CoreSight DAP Lite Errata List - PDF	N	Within ten working days of Annex Effective Date
***	CoreSight DAP Lite TRM - FrameMaker	D	Within ten working days of Annex Effective Date
***	CoreSight DAP Lite TRM - PDF	N	Within ten working days of Annex Effective Date

Section 2

Architecture Documentation

Part Number	Description	Disclosure Rights	Delivery Date
***	ARMv7-A -R Architecture Reference Manual	N	Within ten working days of Annex Effective Date
***	ARMv7-AR Debug Supporting Documentation	N	Within ten working days of Annex Effective Date
***	ARMv7-A -R Architecture Errata List	N	Within ten working days of Annex Effective Date
***	ARMv7-A -R Architecture Release Note	N	Within ten working days of Annex Effective Date

PART B IMPLEMENTATION & INTEGRATION

Part Number	Description	Disclosure Rights	Delivery Date
***	Release Notes	D	Within ten working days of Annex Effective Date
***	Configuration and Signoff Guide	D,CS	Within ten working days of Annex Effective Date
***	Integration Manual - PDF	D	Within ten working days of Annex Effective Date
***	Integration Manual - FrameMaker	D	Within ten working days of Annex Effective Date
***	CoreSight DAP Lite Release Note - PDF	D,CS	Within ten working days of Annex Effective Date
***	CoreSight Generic Components IG - PDF	D,CS	Within ten working days of Annex Effective Date

PART C VERILOG MODELS

Section 1 Synthesizable RTL

Part Number	Description	Disclosure Rights	Delivery Date
***	Synthesizable Verilog RTL	D	Within ten working days of Annex Effective Date
***	APB Access Port Verilog RTL	D	Within ten working days of Annex Effective Date
***	APBMUX for DAP Verilog RTL	D	Within ten working days of Annex Effective Date
***	Serial Wire JTAG dualmode Debug Port RTL	D	Within ten working days of Annex Effective Date
***	CoreSight DAP Lite Verilog RTL	D	Within ten working days of Annex Effective Date

Section 2 Implementation Scripts

Part Number	Description	Disclosure Rights	Delivery Date
***	Synopsys Reference Implementation Flow	D	Within ten working days of Annex Effective Date
***	Cadence Reference Implementation Flow	D	Within ten working days of Annex Effective Date
***	CoreSight DAP Lite LEC Formality	D	Within ten working days of Annex Effective Date
***	CoreSight DAP Lite LEC Conformal	D	Within ten working days of Annex Effective Date
***	CoreSight DAP Lite Synthesis Scripts	D	Within ten working days of Annex Effective Date

Section 3 IP Description

Part Number		Description		Disclosure Rights		Delivery Date
***		IP-XACT Description		D		Within ten working days of Annex Effective Date

PART D RTL TEST BENCHES

Part Number	Description	Disclosure Rights	Delivery Date
***	RAM Integration Test Bench	D	Within ten working days of Annex Effective Date
***	Vector Capture and Replay Test Bench	D,M,T,CS	Within ten working days of Annex Effective Date

N/A

PART E AVS

N/A

PART F FUNCTIONAL TEST VECTORS

Part Number		Description		Disclosure Rights		Delivery Date
***		CoreSight DAP Functional CRF		D,M,T,CS		Within ten working days of Annex Effective Date

PART G FUNCTIONAL & INTEGRATION TEST

Part Number	Description	Disclosure Rights	Delivery Date
***	Portable Functional Test Source	D,M,T,CS	Within ten working days of Annex Effective Date
***	Portable Maximum Power Test Source	D,M,T,CS	Within ten working days of Annex Effective Date
***	Portable Power Indicative Test Source	D	Within ten working days of Annex Effective Date
***	Integration Kit	D,M,T,CS	Within ten working days of Annex Effective Date

PART H MODELS

Part Number	Description	Disclosure Rights	Delivery Date
***	DSM Synopsys VCS Verilog Solaris	N	Within ten working days of Annex Effective Date
***	DSM Synopsys VCS Verilog Linux	N	Within ten working days of Annex Effective Date
***	DSM Synopsys VCS Verilog Solaris 64bit	N	Within ten working days of Annex Effective Date
***	DSM Synopsys VCS Verilog Linux AMD 64bit	N	Within ten working days of Annex Effective Date
***	DSM ModelSim Verilog Solaris	N	Within ten working days of Annex Effective Date
***	DSM ModelSim Verilog Linux	N	Within ten working days of Annex Effective Date
***	DSM ModelSim Verilog Solaris 64bit	N	Within ten working days of Annex Effective Date
***	DSM ModelSim Verilog Linux AMD 64bit	N	Within ten working days of Annex Effective Date
***	DSM NC Verilog Solaris	N	Within ten working days of Annex Effective Date
***	DSM NC Verilog Linux	N	Within ten working days of Annex Effective Date
***	DSM NC Verilog Solaris 64bit	N	Within ten working days of Annex Effective Date
***	DSM NC Verilog Linux AMD 64bit	N	Within ten working days of Annex Effective Date

PART I TECHNICAL NOTES

ISA is ARMv7A

Memory Architecture is Harvard

Pipeline length is 8 stages

SECTION 1.2 - CORTEX-A5 MP

PART A TECHNICAL REFERENCE DOCUMENTS

Section 1

Technical Reference Manuals

Part Number	Description	Disclosure Rights	Delivery Date
***	Technical Reference Manual - PDF	N	Within ten working days of Annex Effective Date
***	Technical Reference Manual - FrameMaker	D	Within ten working days of Annex Effective Date
***	Errata List	N	Within ten working days of Annex Effective Date
***	Supplementary Datasheet	D,CS	Within ten working days of Annex Effective Date
***	CoreSight DAP Lite Errata List - PDF	N	Within ten working days of Annex Effective Date
***	CoreSight DAP Lite TRM - FrameMaker	D	Within ten working days of Annex Effective Date
***	CoreSight DAP Lite TRM - PDF	N	Within ten working days of Annex Effective Date

Section 2

Architecture Documentation

Part Number	Description	Disclosure Rights	Delivery Date
***	ARMv7-A -R Architecture Reference Manual	N	Within ten working days of Annex Effective Date
***	ARMv7-AR Debug Supporting Documentation	N	Within ten working days of Annex Effective Date
***	ARMv7-A -R Architecture Errata List	N	Within ten working days of Annex Effective Date
***	ARMv7-A -R Architecture Release Note	N	Within ten working days of Annex Effective Date

PART B IMPLEMENTATION & INTEGRATION

Part Number	Description	Disclosure Rights	Delivery Date
***	Release Notes	D	Within ten working days of Annex Effective Date
***	Configuration and Signoff Guide	D,CS	Within ten working days of Annex Effective Date
***	Integration Manual - PDF	D	Within ten working days of Annex Effective Date
***	Integration Manual - FrameMaker	D	Within ten working days of Annex Effective Date
***	CoreSight DAP Lite Release Note - PDF	D,CS	Within ten working days of Annex Effective Date
***	CoreSight Generic Components IG - PDF	D,CS	Within ten working days of Annex Effective Date

PART C VERILOG MODELS

Section 1 Synthesizable RTL

Part Number	Description	Disclosure Rights	Delivery Date
***	Synthesizable Verilog RTL	D	Within ten working days of Annex Effective Date
***	APB Access Port Verilog RTL	D	Within ten working days of Annex Effective Date
***	APBMUX for DAP Verilog RTL	D	Within ten working days of Annex Effective Date
***	Serial Wire JTAG dualmode Debug Port RTL	D	Within ten working days of Annex Effective Date
***	CoreSight DAP Lite Verilog RTL	D	Within ten working days of Annex Effective Date

Section 2 Implementation Scripts

Part Number	Description	Disclosure Rights	Delivery Date
***	Synopsys Reference Implementation Flow	D	Within ten working days of Annex Effective Date
***	Cadence Reference Implementation Flow	D	Within ten working days of Annex Effective Date
***	CoreSight DAP Lite LEC Formality	D	Within ten working days of Annex Effective Date
***	CoreSight DAP Lite LEC Conformal	D	Within ten working days of Annex Effective Date
***	CoreSight DAP Lite Synthesis Scripts	D	Within ten working days of Annex Effective Date

Section 3 IP Description

Part Number		Description		Disclosure Rights		Delivery Date
***		IP-XACT Description		D		Within ten working days of Annex Effective Date

PART D RTL TEST BENCHES

Part Number	Description	Disclosure Rights	Delivery Date
***	RAM Integration Test Bench	D	Within ten working days of Annex Effective Date
***	Vector Capture and Replay Test Bench	D,M,T,CS	Within ten working days of Annex Effective Date

N/A

PART E AVS

N/A

PART F FUNCTIONAL TEST VECTORS

Part Number		Description		Disclosure Rights		Delivery Date
***		CoreSight DAP Functional CRF		D,M,T,CS		Within ten working days of Annex Effective Date

PART G FUNCTIONAL & INTEGRATION TEST

Part Number	Description	Disclosure Rights	Delivery Date
***	Portable Functional Test Source	D,M,T,CS	Within ten working days of Annex Effective Date
***	Portable Maximum Power Test Source	D,M,T,CS	Within ten working days of Annex Effective Date
***	Portable Power Indicative Test Source	D,M,T,CS	Within ten working days of Annex Effective Date
***	Integration Kit	D,M,T,CS	Within ten working days of Annex Effective Date

PART H MODELS

Part Number	Description	Disclosure Rights	Delivery Date
***	DSM Synopsys VCS Verilog Solaris	N	Within ten working days of Annex Effective Date
***	DSM Synopsys VCS Verilog Linux	N	Within ten working days of Annex Effective Date
***	DSM Synopsys VCS Verilog Solaris 64bit	N	Within ten working days of Annex Effective Date
***	DSM Synopsys VCS Verilog Linux AMD 64bit	N	Within ten working days of Annex Effective Date
***	DSM ModelSim Verilog Solaris	N	Within ten working days of Annex Effective Date
***	DSM ModelSim Verilog Linux	N	Within ten working days of Annex Effective Date
***	DSM ModelSim Verilog Solaris 64bit	N	Within ten working days of Annex Effective Date
***	DSM ModelSim Verilog Linux AMD 64bit	N	Within ten working days of Annex Effective Date
***	DSM NC Verilog Solaris	N	Within ten working days of Annex Effective Date
***	DSM NC Verilog Linux	N	Within ten working days of Annex Effective Date
***	DSM NC Verilog Solaris 64bit	N	Within ten working days of Annex Effective Date
***	DSM NC Verilog Linux AMD 64bit	N	Within ten working days of Annex Effective Date

PART I TECHNICAL NOTES

ISA is ARMv7A

Memory Architecture is Harvard

Pipeline length is 8 stages

SECTION 1.3 - CORTEX-A5 MPE NEON

PART A TECHNICAL REFERENCE DOCUMENTS

Part Number	Description	Disclosure Rights	Delivery Date
***	Release Notes	D	Within ten working days of Annex Effective Date
***	Technical Reference Manual - PDF	N	Within ten working days of Annex Effective Date
***	Technical Reference Manual - FrameMaker	D	Within ten working days of Annex Effective Date
***	Errata List	N	Within ten working days of Annex Effective Date

PART B IMPLEMENTATION & INTEGRATION

N/A

PART C VERILOG MODELS

Part Number		Description		Disclosure Rights		Delivery Date
***		Synthesizable Verilog RTL		D		Within ten working days of Annex Effective Date

PART D RTL VALIDATION AND VERIFICATION

N/A

PART E AVS

N/A

PART F FUNCTIONAL TEST VECTORS

N/A

PART G FUNCTIONAL & INTEGRATION TEST

Part Number		Description		Disclosure Rights		Delivery Date
***		Portable Functional Test Source		D		Within ten working days of Annex Effective Date

SECTION 1.4 - CORTEX-A5 FPU

PART A TECHNICAL REFERENCE DOCUMENTS

Part Number	Description	Disclosure Rights	Delivery Date
***	Release Notes	D	Within ten working days of Annex Effective Date
***	Technical Reference Manual - PDF	N	Within ten working days of Annex Effective Date
***	Technical Reference Manual - FrameMaker	D	Within ten working days of Annex Effective Date
***	Errata List	N	Within ten working days of Annex Effective Date

PART B IMPLEMENTATION & INTEGRATION

N/A

PART C VERILOG MODELS

Part Number		Description		Disclosure Rights		Delivery Date
***		Synthesizable Verilog RTL		D		Within ten working days of Annex Effective Date

PART D RTL VALIDATION AND VERIFICATION

N/A

PART E AVS

N/A

PART F FUNCTIONAL TEST VECTORS

N/A

PART G FUNCTIONAL & INTEGRATION TEST

Part Number		Description		Disclosure Rights		Delivery Date
***		Portable Functional Test Source		D		Within ten working days of Annex Effective Date

SECTION 2 - LICENCE AND SPECIAL CONDITIONS

A. Definitions

A.1 “Architecture” means the architecture identified in Section 1 Parts I of this Annex 1.

A.2 “Architecture Documentation” means the architecture documentation identified in Section 1 Parts A Section 2 of this Annex 1.

A.3 “ARM Compliant Core” means

(1) with respect to the Cortex-A5MP Core, subsystem as described and identified in the Technical Reference Manual in Section 1.1 of this Annex 1 and which;

(i) contains up to a maximum of four (4) integer CPUs, each of which;

(a) executes each and every instruction in the ARM Instruction Set;

(b) executes no additional instructions to those contained in the ARM Instruction Set;

(c) executes all instructions at an identical rate of cycles per instruction (“CPI”) to that specified in the Technical Reference Manual;

(d) exhibits the Architecture;

(e) exhibits the Pipeline Length; and

(f) is Single Issue;

(ii) implements the programmer’s model as identified in the Technical Reference Manual;

(iii) runs and passes the Functional and Integration Test;

(iv) implements the snoop control unit which controls data cache coherence in the manner described in the Technical Reference Manual;

(viii) integrates the local peripheral, interrupt control and dispatch blocks as described in the Technical Reference Manual; and

(ix) has been verified in accordance with the provisions of Section 3 of this Annex 1.

(2) with respect to the Cortex-A5UP Core, means the microprocessor core as described and identified in the Technical Reference Manual in Section 1.2 of this Annex 1 and which;

(i) executes each and every instruction in the ARM Instruction Set;

(ii) executes no additional instructions to those contained in the ARM Instruction Set;

(iii) exhibits the Architecture;

(iv) exhibits the Pipeline Length;

(v) is Single Issue;

(vi) executes all instructions at an identical rate of cycles per instruction (“CPI”) to that specified in the Technical Reference Manual;

(vii) implements the programmer’s model as identified in the Technical Reference Manual;

(viii) runs and passes the Functional and Integration Test; and

(ix) has been verified in accordance with the provisions of Section 3 of this Annex 1.

A.4 “ARM Compliant Product” means any product designed by or for LICENSEE which has at a minimum an ARM Compliant Core and may also have either a Cortex-A5 FPU or Cortex-A5 NEON.

A.5 Intentionally blank.

A.6 “ARMv7 Instruction Set” means the ARMv7A application processor instruction sets as described in the Architecture Documentation.

A.7 “ARM Instruction Set” means the instruction set identified in Section 1 Parts I of this Annex 1.

A.8 “Cortex-A5 MP Core” means the Cortex-A5 MP core as described and identified in the Technical Reference Manual in Section 1.2 of this Annex 1.

A.9 “Cortex-A5 UP Core” means the Cortex-A5 MP core as described and identified in the Technical Reference Manual in Section 1.1 of this Annex 1.

A.10 “Cortex-A5 NEON” means the Cortex-A5 NEON as described and identified in the Technical Reference Manual in Section 1.3 of this Annex 1.

A.11 “Cortex-A5 FPU” means the Cortex-A5 FPU as described and identified in the Technical Reference Manual in Section 1.4 of this Annex 1.

A.11A “Design Start” means the earlier of any of the following; (i) the date that LICENSEE first synthesises the Synthesisable RTL for an ARM Compliant Product; (ii) the date that LICENSEE enters into a contract with a third party for the design of an ARM Compliant Product; or (iii) the date that LICENSEE delivers any ARM Technology or derivatives thereof, to a Customer pursuant to the licenses granted in this Annex 1.

A.11B “Download” means the removal or copying of any or all of the relevant ARM Technology in respect of each ARM Compliant Product from the secure area on xxx.xxxxxxx.xxx.xxx.

A.12 “End User Licence” means a license agreement substantially in the form set out in Section 10 of this Annex 1.

A.13 “Functional and Integration Test” means the relevant test files identified in Section 1 Part G of this Annex 1.

A.14 “Functional Test Vectors” means the functional test vectors identified in Section 1 Part F of this Annex 1.

A.15 “Harvard Architecture” means a microprocessor architecture which dictates that the address and data memory system for instruction fetches and for data load/store operations are separate.

A.16 “Implementation and Integration Documentation” means the documentation identified in Section 1 Part B of this Annex 1.

A.17 “Implementation Scripts” means the deliverables identified in Section 1 Part C Section 2 of this Annex 1.

A.18 “IP-XACT Descriptions” means the deliverables identified in Section 1 Part C Subsection 3.

A.19 “Models” means; (i) the design simulation models identified in Section 1 Part H; and (ii) any other design simulation model for the Cortex-A5 MPCore or Cortex-A5UP Core which are generally available from ARM subject to; (a) receipt by ARM of a purchase order from LICENSEE requesting such design simulation model expressly subject to the terms and conditions of this Agreement; and (b) the payment by LICENSEE to ARM of the then current fee for such design simulation model as quoted by ARM from time to time.

A.20 “Pipeline Length” means the number of clocked stages through which each single-cycle instruction must pass to complete the execution of such instruction and identified in Section 1 Part I of this Annex 1and which is partitioned with three stages occurring in prefetch.

A.21 “RTL Test Benches” means the program files identified in Part D of this Annex 1.

A.22 “Single Issue” means that only one instruction is issued for execution within the integer unit in any single clock cycle, where for the purposes of this definition clock means the clock that advances the pipeline.

A.23 “Synthesisable RTL” means the deliverables identified in Section 1 Part C Section 1 of this Annex 1.

A.24 “Technical Reference Manual” means the relevant technical reference manuals identified in Section 1 Part A Section 1 of this Annex 1.

A.26 “Unique ARM Compliant Product” means:

(i) an unlimited number of units of a single design for an ARM Compliant Product which has been taped out and given a unique part number; and

(ii) an unlimited number of units of any derivatives of the ARM Compliant Products referred to in Clause A.26(i), provided that:

(a) such derivatives result only from any or all of the following modifications; (1) the implementation by LICENSEE of an Update delivered by ARM to some or all of the ARM Technology; (2) the correction of errors in such ARM Compliant Products to achieve conformance with the original specification for such design; and (3) a version of such ARM Compliant Product that has been ported to a different set of process design rules but is otherwise functionally unmodified (except to the extent accommodated by this definition); and

(b) except as provided below, no more than one such derivative for the ARM Compliant Product referred to in Clause A.26(i) is being manufactured for LICENSEE at any time. LICENSEE shall be permitted to concurrently manufacture the derivative and the design from which such derivative was derived; (i) indefinitely if the derivative is a result of Clause A.26(ii)(a)(1) or Clause A.26(ii)(a)(2); and (ii) if the derivative is a result of Clause A.26(ii)(a)(3), then for a period of six (6) months from the date of first manufacture of the new derivative.

A.27 “Use” means in respect of the object code of the Models, the use of (including copying the object code of the Models to the extent that such copying is incidental to such use, including installation, backup and execution) the object code of the Models, or any part thereof. Use shall specifically exclude: (i) the translation, adaptation, arrangement or other alteration of the object code of the Models except as allowed by local legislation implementing Article 6 of the EC Directive on the legal protection of computer programs (91/250/EEC) and then only to the extent necessary to achieve interoperability of an independently created program with other programs; and (ii) the adapting or reverse compiling of the object code of the Models for the purpose of error correction.

B. Licence

B.1 Subject to the provisions of Clause 3 (Confidentiality) of the TLA and the provisions of this Section 2, ARM hereby grants, to LICENSEE, a non-transferable (subject to Clause 16.3 of the TLA), non-exclusive, world-wide licence for the Term to;

Technical Reference Manuals

(i) use, copy, modify (solely to the extent necessary to reflect any permitted modifications in accordance with the provisions of this Clause B.1 or for incorporation into LICENSEE’s documentation), distribute and have distributed the Technical Reference Manuals;

(ii) use and copy the Architecture Documentation for the purpose of designing and having designed (subject to the provisions of Clause 2.2 of the TLA) ARM Compliant Products;

ARM Compliant Core

(iii) use and copy the Implementation and Integration Documentation only for the purposes of designing and having designed (subject to the provisions of Clause 2.2 of the TLA) ARM Compliant Products;

(iv) use, copy and modify (solely for the purposes of scan insertion, buffer insertion, timing closure, targeting standard cell libraries, direct instantiations of cells for speed or power or area optimisation, use of licensee specified BIST and changing any “Verilog Defines” which are stated as being modifiable in the Implementation and Integration Documentation and changing any configuration settings permitted in the relevant Implementation and Integration Documentation) the Synthesisable RTL, only for the purposes of designing and having designed (subject to the provisions of Clause 2.2 of the TLA) ARM Compliant Products;

(v) use, copy and modify the Implementation Scripts and IP-XACT Descriptions (if applicable) only for the purposes of designing and having designed (subject to the provisions of Clause 2.2 of the TLA) ARM Compliant Products;

(vi) use, copy and modify the Functional and Integration Test only for the purposes of designing and having designed (subject to the provisions of Clauses 2.2 and 2.3 of the TLA) ARM Compliant Products;

(vii) use, copy and modify (solely for the purpose of and to the extent necessary to run the vectors on a simulator or tester) the Functional Test Vectors, only for the purposes of designing and having designed (subject to the provisions of Clauses 2.2 and 2.3 of the TLA), manufacturing and having manufactured (subject to the provisions of Clause 2.4 of the TLA), testing and having tested (subject to the provisions of Clause 2.5 of the TLA) ARM Compliant Products;

(viii) use, copy and modify the RTL Test Benches only for the purposes of designing and having designed (subject to the provisions of Clause 2.2 of the TLA) ARM Compliant Products;

(ix) manufacture and have manufactured (subject to the provisions of Clause 2.4 of the TLA) the Unique ARM Compliant Products created under the licences granted in Clauses B.1(i) to B.1(viii) inclusive;

(x) test and have tested (subject to the provisions of Clause 2.5 of the TLA) the Unique ARM Compliant Products manufactured under the licences granted in Clause B.1(ix);

(xi) package and have packaged (subject to the provisions of Clause 2.6 of the TLA), the Unique ARM Compliant Products manufactured under the licences granted in Clause B.1(ix);

(xii) sell, supply and distribute encapsulated die of the Unique ARM Compliant Products which have been manufactured and packaged under the licences granted in Clause B.1(ix) and B.1(xi) ;

Models

(xiii) copy and use, internally and for third party support purposes, the Models and related documentation;

(xiv) use, reproduce and distribute, and sub-license (subject to the terms of an End User Licence) the Use of the object code of the Models, solely for the purpose of developing ARM Compliant Products; and

(xv) modify, reproduce, use and distribute, in connection with the Models, the documentation related thereto.

C. Confidentiality

C.1 Notwithstanding the confidentiality provisions set out in Clause 3.5 of the TLA, LICENSEE may disclose any vectors created by or for LICENSEE and which have been derived from the Functional and Integration Test (“Derived Vectors”), to a Test House under a non-disclosure agreement containing substantially similar terms to Clause 3 of the TLA, except that the confidentiality period shall be, at a minimum, five (5) years from the date of disclosure to the Test House.

The Test House shall only be permitted to use the Derived Vectors for the purposes of testing ARM Compliant Products. The parties hereby agree that the foregoing shall be treated as a “have tested right” and accordingly the provisions of Clause 2.5 shall apply in respect of any disclosures of Derived Vectors to a Test House.

D. Special Conditions

Sun Java Hardware Acceleration

“Sun SCSL License Agreement” means any of; (i) a Sun Community Source License entered into between LICENSEE and Oracle America, Inc. (fka Sun Microsystems Inc.) for the Sun CLDC technology; or (ii) any license agreement entered into between LICENSEE and Oracle America, Inc. which expressly permits LICENSEE to share source code with ARM for the Sun CLDC technology.

“Jazelle” means the extension to the ARM architecture that enables the execution of a subset of Java byte codes by an ARM core as accessed through the BXJ instruction.

D.1 LICENSEE acknowledges that the ARM Compliant Core incorporates hardware acceleration for Oracle America, Inc.’s Java technology. Without prejudice to any limitations or restrictions set out in the licence grants in Clause B.1 above, LICENSEE agrees that unless LICENSEE has entered into and continues to enjoy the benefit of a Sun SCSL License Agreement, LICENSEE shall be subject to the following licensing restrictions;

A. LICENSEE shall not; (i) carry out or procure any functional modification of any part of the Cortex-A5MP Core or Cortex-A5UP Core to the extent that it includes, incorporates or implements Jazelle; or (ii) reverse engineer or use the ARM Technology licensed under this Annex for the purpose of implementing the whole or any part of a Java specification (where a Java specification means any “Final Release” of a “JSR” developed as part of the Java Community Process without first entering into a Sun SCSL License Agreement;

B. LICENSEE agrees that Oracle America, Inc. shall be an intended third party beneficiary of the terms and conditions of this TLA solely for the purpose of enforcing the restrictions contained in A above; and

C. If LICENSEE discloses or distributes any ARM Technology which includes, incorporates or implements Jazelle to a third party, except as ARM Compliant Products in the form of silicon, then such third party shall be made subject to the same restrictions as LICENSEE in A and B above.

E. Disclosures

Clause E.1 applies to the Cortex-A5UP Core and the Cortex-A5 MP Core.

E.1 Notwithstanding that the following suit was not commenced against ARM but resulted from ARM’s intervention, ARM hereby discloses the following against the warranty provided in Clause 11.1(ii) of the TLA:

On the 21 June 2010 ARM’s motion to intervene in the patent infringement suit between Nazomi Communications, Inc. (Plaintiff) and Nokia Corporation et al (Defendants) [Case SA CV 10-151-DOC (RNBx)]in the United States District Court for the Central District of California was granted. The case has been transferred to the Northern District of California [5:10-cv-04686-JF]. The Plaintiff alleges that electronic devices containing processor cores, licensed by ARM and capable of Java hardware acceleration, infringe US Patents 7,080,362 and 7,225,436.

F. IP access model Provisions

Number of Unique ARM Compliant Products

F.1 Under this Annex 1, LICENSEE shall have the right to exercise the licenses granted under Clause B.1 of this Annex 1 for an unlimited number of Unique ARM Compliant Products, provided that for each such Unique ARM Compliant Product LICENSEE pays to ARM the respective Use Fee as set out in, and in accordance with the provisions of Section 8 of this Annex 1.

Audit

F.2 In addition to the audit requirements in Clause 6.6 of the TLA, the Auditors shall be entitled to review; (i) the ARM Technology which has been Downloaded by LICENSEE; (ii) Design Starts for any Unique ARM Compliant Products; and (iii) any information necessary to substantiate and verify the data submitted to ARM by LICENSEE in any Usage Report provided in accordance with Section 8. LICENSEE’s books and records relevant to verification of the information which LICENSEE is obliged to report pursuant to this Clause, shall be retained by LICENSEE for at least six (6) years after the end of the period to which the Download, Design Start or Usage Report relates.

G. LIMITATION OF LIABILITY

G.1 For the purposes of this Annex 1, delete Clause 13.2 of the TLA and replace with the following:

“13.2 NOTWITHSTANDING ANYTHING TO THE CONTRARY CONTAINED IN THIS TLA, THE MAXIMUM LIABILITY OF ARM TO LICENSEE IN AGGREGATE FOR ALL CLAIMS MADE AGAINST ARM IN CONTRACT TORT OR OTHERWISE UNDER OR IN CONNECTION WITH EACH ARM DELIVERABLE (AS DEFINED BELOW) LICENSED UNDER AN ANNEX 1 SHALL NOT EXCEED THE USE FEES PAID

TO ARM IN RESPECT OF THAT ARM DELIVERABLE. THE EXISTENCE OF MORE THAN ONE CLAIM OR SUIT WILL NOT ENLARGE OR EXTEND THE LIMIT. LICENSEE RELEASES ARM FROM ALL OBLIGATIONS, LIABILITY, CLAIMS OR DEMANDS IN EXCESS OF THIS LIMITATION”

“ARM Deliverable” means an individual product being part of the ARM Technology delivered under an Annex 1 where such product has an associated Use Fee in Section 8 of the relevant Annex 1.

SECTION 3 - VERIFICATION

V.1 Definitions

V.1.1 “Implementation” means, (i) with respect to the Cortex-A5UP Core, the microprocessor core, a unique physical layout for such microprocessor core and (ii) with respect to the Cortex-A5MP Core, the multiprocessor core, a unique physical layout for such microprocessor core.

V.1.2 “RAM Integration Test Bench” means the test bench identified as part of the RTL Test Benches part number *** for Cortex-A5 MP Core and *** for Cortex-A5 UP Core.

V.1.3 “Post Layout Synthesized Netlist” means a post layout synthesized netlist incorporating the ARM Compliant Core which; (i) obeys the Timing Constraints File in respect of such synthesis; and (ii) includes back annotated delays derived from the physical layout.

V.1.4 “Power-On Reset” means the reset mode of the ARM Compliant Core that is performed when power is first applied to the system.

V.1.5 “Timing Constraints File” means the timing constraints file determined by LICENSEE prior to final synthesis.

V.1.6 “Verification Confirmation” means the completed document in the form set out in Part C of Section 3 of this Annex 1.

V.2 Verification of ARM Compliant Core Implementation

V.2.1 For each Implementation of an ARM Compliant Core intended for incorporation in integrated circuits which will be distributed by or for LICENSEE, LICENSEE shall verify such Implementation by at least one of the following methods;

1. Verification by Equivalence Checking of RTL and Synthesized Netlist (See Part A)

3. LICENSEE Specified verification (See Part B)

Part A

Verification by Equivalence Checking of RTL and Synthesized Netlist

Methodology

Validation

V.A.1 Validate the Synthesisable RTL using the RAM Integration Test Bench in accordance with the Implementation and Integration Documentation and generate the validation log report (“Validation Logs”).

Verification

V.A.2 (i) use an equivalence checker to compare the Synthesisable RTL with the Post-Layout Synthesized Netlist and generate equivalence check log results (“RTL-Post Layout Equivalence Log Results”); (ii) run static timing analysis on the Post-Layout Synthesized Netlist and generate log results (“STA Log Results”); and (iii) simulate functional code on the Post-Layout Synthesized Netlist that will at least boot the ARM Compliant Core by performing a Power-On Reset and generate log results (“Post Layout Log Results”).

Delivery of Verification Confirmation

V.A.3 If the Validation Logs, RTL-Post Layout Equivalence Log Results, Post Layout Log Results and the STA Log Results (together the “Equivalence Log Results”) indicate that no errors have been detected (or the parties have jointly agreed a waiver in respect of any detected errors), LICENSEE shall deliver a Verification Confirmation to ARM and ARM shall acknowledge, in writing, the receipt by ARM of the Verification Confirmation within ten (10) working days of its receipt by ARM.

Verification Criteria

V.A.4 The Implementation of the ARM Compliant Core shall be verified when; (i) the Equivalence Log Results indicate that no errors have been detected (or the parties have jointly agreed a waiver in respect of any detected errors); and (ii) LICENSEE has received confirmation of receipt of the relevant Verification Confirmation from ARM in accordance with the provisions of Clause V.A.3.

Records and Delivery of Equivalence Log Results

V.A.5 For each ARM Compliant Product incorporating an Implementation of the ARM Compliant Core, LICENSEE shall keep a copy of the Equivalence Log Results for such ARM Compliant Product and shall deliver, as soon as reasonably possible, copies of such records to ARM upon request from ARM. If ARM reasonably concludes that the Implementation of the ARM Compliant Core has not been verified in accordance with the provisions of Clause V.A.4, then ARM shall indicate to LICENSEE the errors which ARM has detected and LICENSEE shall repeat the process prescribed in Clauses V.A.1- V.A.4.

Part B

LICENSEE Specified Verification

Methodology

V.B.1 Subject to V.B.4, use LICENSEE’s custom verification flow.

V.B.2 If LICENSEE elects such verification, LICENSEE shall, inform ARM in writing at least ninety (90) days prior to tape out of an ARM Compliant Product that LICENSEE wishes to use LICENSEE’s specified verification flow and supply to ARM a copy of the proposed verification flow (each a “Verification Flow”). Within 30 days of the receipt of the Verification Flow ARM shall notify LICENSEE in writing whether the Verification Flow has been accepted by ARM, which acceptance shall not be unreasonably withheld. If accepted by ARM, LICENSEE shall verify such ARM Compliant Products using the Verification Flow. If after acceptance of the Verification Flow by ARM, LICENSEE wishes to modify the Verification Flow LICENSEE shall submit the modified Verification Flow to ARM for re-acceptance prior to verifying the relevant Synthesisable ARM Compliant Core.

V.B.3 If ARM rejects either the Verification Flow or any modified Verification Flows, ARM shall provide LICENSEE with written reasons for such rejection together with any required changes. LICENSEE may resubmit the Verification Flow or any modified versions thereof to ARM for acceptance.

Default

V.B.4 If ARM fails to either accept or reject the Verification Flow within 30 days of ARM’s receipt of the Verification Flow from LICENSEE, then the relevant ARM Compliant Core shall be deemed verified.

Part C

Verification Confirmation

Verification in accordance with Section 3 Part A

1. RAM Integration Test Bench

Description of process applied		Tool(s) used		Completed (Tick)
Running RAM Integration Test Bench

2 Equivalence checking

Description of process applied		Tool(s) used		Completed (Tick)
ARM Compliant Core RTL to post-layout netlist *

* Process can be performed in one step or using several intermediate steps

3. STA on Post-Layout Synthesized Netlist

Description of process applied		Tool(s) used		Completed (Tick)
Post-layout netlist

Verification in accordance with Section 3 Part B

Depending upon agreed verification methodology.

Partner
Partner Contact
Design name / number / ID
Process name
Library name
Core Name and Revision
Date
Signature

SECTION 4 - SUPPORT LIMITATION

4.1 Except as provided below, the maximum number of man hours that ARM shall be obligated to expend on any individual support case submitted to ARM by LICENSEE shall be capped at sixteen (16).

4.2 If ARM reasonably believes that any individual support case will exceed the support cap referred to above, ARM and LICENSEE will mutually agree a plan of action for resolution of the support case.

4.3 If a support case results in a defect being identified, any time associated with correcting such defect will not be logged against such support case.

4.4 If ARM, at ARM’s discretion, determines that LICENSEE has entered multiple cases which relate to the same support problem, ARM shall be entitled to compile these into a single case which in aggregate will be subject to the cap referred to above.

4.5 If ARM agrees to provide support at LICENSEE’s premises in accordance with the provisions of Clause 7.3 of the TLA, any time spent at LICENSEE’s premises including travel shall not be included as part of the support cap.

SECTION 5 - TRAINING REQUIREMENT

Subject to the payment of the Training Fee (set out in Section 8 of this Annex 1), ARM shall make available the following training to LICENSEE

Training Course		Commencement Date		Course Length (Days)		Number of Permitted Trainees
Standard core implementation training course for Cortex-A5 to be held at LICENSEE’s premises in China.		Within 12 months of Annex Effective Date		4		12

SECTION 6 - TRADEMARKS

Trademark		Registered/ Unregistered

Part A

ARM w/bar [logo] Exhibit A		Registered

Part B

ARM Powered [logo] Exhibit B		Registered

Part C

ARM [logo] Exhibit C		Registered

Part D

ARM Connect Community Partner [logo] Exhibit D		Registered

Part E

ARM		Registered
MPCore		Unregistered
UPCore		Unregistered

SECTION 7 - TERM

Unless terminated earlier in accordance with the provisions of Clause 14 of the TLA, this Annex 1 shall continue in force for a period of three (3) years

SECTION 8 - FEES AND ROYALTIES

FEES

PRODUCT ANNEXES MEANS THE FOLLOWING ANNEXES:

No.	Product	Domino
1	Cortex-A5 MPCore / UP / FPU / NEON	LES-ANX-20356
2	Coresight DK- A5	LES-ANX-20355
3	Mali 300	LES-ANX-20354
4	AMBA Designer Configurable system products Fixed system products	LES-ANX-20353
5	PIPD — POP and cells	LES-ANX-20348
6	PIPD - compilers	LES-ANX-20349

In consideration of ARM delivering the ARM Technology licensed under the Product Annexes to LICENSEE, LICENSEE shall pay to ARM a non-refundable, pre-paid license fee (the “Pre-Paid License Fee”) in accordance with the table set out below;

	US$
Fee (Descriptor)	Due	Payable	Due Date (Invoice Date)

Pre-Paid Licence Fee	***	***	Annex Effective Date
		***	5 months after Annex Effective Date
Training Fee	***	***	Annex Effective Date

Use Fees

The following table sets out the Use Fees payable for the ARM technology licensed under the Products Annexes-

Annex Number	Product	Use Fee (US$)

	Cortex A5 UP per-use license	***
	Cortex A5 MP per-use license	***
	Cortex A5 NEON coprocessor per-use license	***
	Cortex A5 FPU coprocessor per-use license	***
	Coresight DK-A5 per-use license	***

	NIC-301 AMBA 3 Interconnect	***
	L2C-310 Level 2 Cache Controller	***
	AMBA Designer 1 seat/year	***
	QoS301 AMBA 3 Interconnect	***
	DMC-400 DDR3/LPDDR2 Memory Controller	***
	GIC-390 Generic Interrupt Controller	***
	SMC-353 NAND, NOR, SRAM Memory Controller	***

	Mali-300 per-use license	***

	Cortex A5 High Performance Optimization Package	***
	Logic Multi-Channel 12-track
	SC12MC High Performance MC Standard Cell Library RVt C50	***
	SC12MC High Performance MC Standard Cell Library HVT C50	***
	SC12MC High Performance MC Standard Cell Library LVt C50	***
	SC12MC High Performance MC Standard Cell Power Management Kit RVT C50-HVTC50	***
	SC12MC High Performance MC Standard Cell ECO Kit RVt C40	***

	Logic Multi-Channel 9-track
	SC9MC High Density MC Standard Cell Library RVt C50	***
	SC9MC High Density MC Standard Cell Library HVT C50	***
	SC9MC High Density MC Standard Cell Library LVt C50	***
	SC9MC High Density MC Standard Cell Power Management Kit	***
	SC9MC High Density MC Standard Cell ECO Kit RVt C40	***

Annex Number	Product	Use Fee (US$)

	Memory Compilers
	High Density Single-port SRAM Compiler	***
	High Density Single-port RF Compiler	***
	High Density Two Port register File Complier	***
	High Density Dual Port SRAM Compiler	***
	High Density Via Programmable ROM Compiler	***

Subject to the provisions of this Section 8, for each Unique ARM Compliant Product developed under this Annex 1, LICENSEE shall pay to ARM the relevant Use Fees set out in the table below:

ARM Technology		Use Fee (US$)

Each Unique ARM Compliant Product containing Cortex-A5 MPCore		See Use Fees Table set out above
Each Unique ARM Compliant Product containing Cortex-A5 UPCore		See Use Fees Table set out above
Each Unique ARM Compliant Product containing Cortex-A5 FPU		See Use Fees Table set out above
Each Unique ARM Compliant Product containing Cortex-A5 NEON		See Use Fees Table set out above

The Use Fee payable to ARM by LICENSEE shall be due to ARM as follows:-

(i) Upon first Download of the ARM Technology for the relevant ARM Compliant Core;

(ii) Upon Design Start of the second and each subsequent Unique ARM Compliant Product incorporating such ARM Compliant Core.

All Use Fees shall be due at the end of the Quarter in which the Download or Design Start has occurred as applicable. Notwithstanding the foregoing, LICENSEE shall not be obligated to pay the whole or any part of any Use Fees, to ARM under the Product Annexes, until such time as the aggregate Use Fees which LICENSEE is obligated to pay to ARM under the Product Annexes has exceeded the amount of the Pre-Paid License Fee that has become due to ARM.

Where any Pre-Paid Licence Fees have not become due, invoices raised by ARM for amounts that exceed the amount of the Pre-Paid Licence Fee that has become due to ARM will be set off against any subsequent milestone payments for the Pre-Paid Licence Fee that have not yet become due to ARM.

Example

On the Annex Effective Date, ARM issues an invoice for $***, first milestone payment for the Pre-Paid Licence Fee. For the purposes of this example, second milestone payment is $*** due five months after Annex Effective Date. After one month, LICENSEE downloads Cortex-A5MP, incurring Use Fees of $***. As the amount of the Pre-Paid Licence Fee due to ARM has been exceeded by $100,000, ARM will issue a further invoice for $***. Provided the invoices for $*** and $*** have been paid by LICENSEE, and no other Use Fees are incurred before the second milestone payment becomes due, LICENSEE will be issued with an invoice for $*** for the second milestone payment of the Pre-Paid Licence Fee, five months after the Annex Effective Date.

Usage Report

Within thirty (30) days of the end of each Quarter, LICENSEE shall submit a report to ARM substantially in the format set out below:

ARM
Technology

Date of
Download

Date of
Design Start

Part
Number of
Unique
ARM
Compliant
Product

Use Fee

Support and
Maintenance
Fee

Fees Due

Access Fees

	Access Fees ($ US)
Product(s)	Year 1*	Year 2**	Year 3***
All technology licensed under the Product Annexes	***	*** (option)	*** (option)

* In respect of the first year of the Term, the Access Fees shall be due on the Annex Effective Date.

** In respect of the second year of the Term, subject to request from LICENSEE, the Access Fees shall be due on the first anniversary of the Annex Effective Date.

*** In respect of the third year of the Term, subject to request from LICENSEE, the Access Fees shall be due on the second anniversary of the Annex Effective Date.

Access to ARM Technology in the Product Annexes

For the avoidance of doubt, LICENSEE will not be able to Download any ARM technology licensed under the Product Annexes during any year of Term unless LICENSEE has paid the Access Fees for the relevant period.

Support and Maintenance Fees

	Support and Maintenance Fees ($ US)
Product(s)	Year 1*	Year 2**	Year 3***
All technology licensed under the Product Annexes	***	*** (option)	*** (option)

* In respect of the first year of the Term, the Support and Maintenance Fees shall be due on the Annex Effective Date.

** In respect of the second year of the Term, subject to request from LICENSEE, the Support and Maintenance Fees shall be due on the first anniversary of the Annex Effective Date.

*** In respect of the third year of the Term, subject to request from LICENSEE, the Support and Maintenance Fees shall be due on the second anniversary of the Annex Effective Date.

Entitlement to Support and Maintenance Services.

In respect of each of the ARM Technology licenced under the Product Annexes, in addition to paying the Access Fee for the relevant period, LICENSEE must pay the Support and Maintenance Fees for the relevant period to be entitled to request Support and Maintenance Services in respect of such ARM Technology licenced under the Product Annexes.

ROYALTIES

Currency: US Dollars

Currency Conversion: ASP in any currency other than US$ shall be converted to ASP in US$ using the average local currency/US$ exchange rate over the Quarter as published by the US Federal Reserve [see xxxx://xxx.xxxxxxxxxxxxxx.xxx/xxxxxxxx/x0/]

Due: At the end of each Quarter

Payable: In accordance with the provisions of Clause 6 of the TLA.

Invoice Address:

Calculation:

For each unit of ARM Compliant Product distributed by LICENSEE, LICENSEE shall pay a Royalty determined from the following table:

	Royalty Rate
Cumulative Number of Units of ARM Compliant Products distributed by LICENSEE under this Annex 1	ARM Compliant Product containing an ARM Compliant Core for Cortex-A5UP Core or for Cortex-A5 MP Core with ONE (1) integer CPU (“Base Royalty”)	ARM Compliant Product containing an ARM Compliant Core for Cortex-A5 MP Core with two (2) integer CPU’s	ARM Compliant Product containing an ARM Compliant Core for Cortex-A5 MP Core with three (3) integer CPU’s	ARM Compliant Product containing an ARM Compliant Core for Cortex-A5 MP Core with four (4) integer CPU’s
0 — 1,000,000	The greater of ***% of ASP and Royalty Floor	*** x Base Royalty Rate	*** x Base Royalty Rate	*** x Base Royalty Rate
1,000,001 — 5,000,000	The greater of ***% of ASP and Royalty Floor	*** x Base Royalty Rate	*** x Base Royalty Rate	*** x Base Royalty Rate
5,000,001 — 10,000,000	The greater of ***% of ASP and Royalty Floor	*** x Base Royalty Rate	*** x Base Royalty Rate	*** x Base Royalty Rate
10,000,001 — 50,000,000	The greater of ***% of ASP and Royalty Floor	*** x Base Royalty Rate	***x Base Royalty Rate	*** x Base Royalty Rate
>50,000,000	The greater of ***% of ASP and Royalty Floor	*** x Base Royalty Rate	*** x Base Royalty Rate	*** x Base Royalty Rate

Where Royalty Floor means US$*** where ASP is greater than or equal to US$*** and US$*** where ASP is less than US$***.

For the purpose of calculating Royalties, only the distribution by the entity exercising the licences to distribute die of ARM Compliant Products which have been manufactured under this Annex 1 (notwithstanding that such distribution may be between RDA and a Subsidiary of RDA or between Subsidiaries of RDA) shall be relevant.

All Royalties paid to ARM pursuant to this Annex 1 shall be non refundable.

In an ARM Compliant Product with more than one ARM core embedded into the same piece of silicon, the royalties for each core in the device shall be cumulated, starting with the cores that have the highest royalty. The total royalty payable on the subsequent cores shall be reduced in accordance with the following table;

Core		% of royalty payable

ARM core with highest royalty		***% of applicable Royalty
ARM core with same or second highest royalty		***% of applicable Royalty
ARM core with same or third highest royalty		***% of applicable Royalty
ARM core with same or fourth highest royalty		***% of applicable Royalty
each subsequent ARM core		***% of applicable Royalty

Note for the purposes of calculating royalties the ARM Compliant Core shall be counted as a single ARM core irrespective of the number of integer CPU’s contained within the subsystem.

ROYALTY REPORT

Form of Royalty Report

Send to: The address for ARM set out in the TLA via first class mail and to xxxxxxxxxxxxxx@xxx.xxx via email.

LICENSEE

LICENSEE contact

Quarter for which report relates to

Table 1

Part
Number

Intended
Application

Number of Units of
ARM Compliant
Product distributed by
LICENSEE in Quarter

ASP (US$)

Applicable Royalty
Rate

Royalty Due

XXX

Table 2

Part
Number

Intended
Application

Estimated Number of
Units of ARM
Compliant Product
distributed by
LICENSEE in Next
Calendar Quarter

ASP (US$)

Applicable Royalty
Rate

Royalty Due

XXX

The information provided in Table 2 shall be non-binding, supplied in good faith and treated as LICENSEE’s Confidential Information.

SECTION 9 — MARKETING

Notwithstanding anything to the contrary contained in the TLA either party may disclose to third parties that LICENSEE is a licensee of the ARM Technology licensed under this Annex 1. Except as expressly provided in the TLA, no right is granted to either party to disclose the terms and conditions of the TLA or this Annex 1.

Within sixty days (60) days of the Annex Effective Date the parties shall mutually agree the terms and method of issuance of a written announcement, which may be a press release, relating to the technology licensed under this Annex 1 and the relationship of the parties.

All communications for the above marketing activities shall be sent to the following contacts:

ARM Marketing Contact		LICENSEE Marketing Contact

Director of Corporate Communications
XxxxxXxxxxxxx@xxx.xxx
000 Xxxxxxxx Xxxx
Cambridge
CB1 9NJ

SECTION 10 — END USER LICENCE

[Respective LICENSEE entity] (“LICENSOR”) hereby grants and the LICENSEE hereby accepts a non transferable and non-exclusive licence to use the Model solely for the purpose of developing a product which incorporates a CPU manufactured under LICENSOR’s licence from ARM (“Purpose”), under the following terms and conditions:

1. Ownership. The Model is the property of ARM LIMITED and/or its licensors. The LICENSEE acquires no title, right or interest in the Model other than the licence rights granted herein.

2. Use. The LICENSEE may use the Model on any one computer at one time except that the Model may be executed from a common disc shared by multiple CPUs provided that one authorised copy of the Model has been licensed from LICENSOR for each CPU concurrently executing the Model.

LICENSEE shall not reverse engineer, decompile or disassemble the Model, in whole or in part.

LICENSEE shall only be permitted to use the Model for the Purpose.

LICESENSOR hereby authorises LICENSEE to concurrently use up to a maximum number of [ ] copies of the Model

3. Copies. Except as provided in Clause 2, LICENSEE may make copies of the Model for back-up and archival purposes only. All copies of the Model must bear the same notice(s) contained on the original copies supplied by LICENSOR.

4. Model Limited Warranty. LICENSOR warrants that the disks containing the Model shall be free from defects and workmanship under normal use and the programs will perform in accordance with the accompanying documentation for a period of ninety (90) days from the date of delivery. Any written or oral information or advice given by LICENSOR distributors, agents or employees will in no way increase the scope of this warranty. LICENSOR’s entire liability and the LICENSEE’s exclusive remedy will be, at LICENSOR’s sole option, to replace the disk or to use LICENSOR’s reasonable efforts to make the Model meet the warranty set forth above. Any replacement Model will be warranted for the remainder of the original warranty period or thirty (30) days, whichever is the longer. The LICENSEE agrees that the supply of the Model does not include updates and upgrades, which may be available from LICENSOR under a separate support agreement.

THE ABOVE WARRANTIES ARE EXCLUSIVE AND IN LIEU OF ALL OTHER WARRANTIES, WHETHER EXPRESS OR IMPLIED INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.

IN NO EVENT SHALL LICENSOR BE LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES RESULTING FROM ITS PERFORMANCE OR FAILURE TO PERFORM UNDER THIS AGREEMENT OR THE FURNISHING, PERFORMANCE, OR USE OF ANY MODEL LICENSED HERETO, WHETHER DUE TO BREACH OF CONTRACT, BREACH OF WARRANTY, OR NEGLIGENCE EVEN IF LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

THE MAXIMUM LIABILITY OF LICENSOR SHALL BE LIMITED TO REFUND OF THE FEES PAID BY LICENSEE (IF ANY) FOR THE MODEL.

5. Assignment of the Agreement. This Agreement and any license granted hereunder to the LICENSEE may not be assigned, sub-licensed or otherwise transferred by the LICENSEE to any third party

6. Term and Termination. Unless terminated in accordance with the provisions of this Clause 6, this Agreement and licenses granted hereunder shall continue in force until completion of the Purpose. LICENSOR may terminate this Agreement by written notice to the LICENSEE in the event of a breach by LICENSEE of any provisions of this Agreement.

Upon expiration or termination of this Agreement, the LICENSEE shall refrain from any further use of the Model, and LICENSEE shall either return or destroy and copies of the Model in it’s possession at the date of expiration of termination as applicable.

7. Applicability. The limitations and exclusions above may not apply in certain countries or states where they conflict with local law. In cases where such a conflict exists the local law shall prevail and the remaining provisions of the Agreement shall remain in full force and effect.

IN WITNESS WHEREOF the parties have caused this Annex 1 to be signed by their duly authorised representative:

ARM LIMITED		RDA TECHNOLOGIES LIMITED


BY:	/s/ Xxxx Xxxxxx	BY:	/s/ Xxxxxxx Xxx

NAME:	Xxxx Xxxxxx	NAME:	Xxxxxxx Xxx

TITLE:	Chief Commercial Officer	TITLE:	CEO

DATE:	27-4-2012	DATE:	2012.2.9

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ANNEX 1 RDA TECHNOLOGIES LIMITED CORTEX-A5 UP / CORTEX-A5MP / CORTEX-A5 FPU / CORTEX-A5 NEON

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