PLL Unit Sample Clauses

PLL Unit. PLL Unit is intended to keep VCO 5MHz phase locked to the maser signal. The Multiplier forms from crystal oscillator signal standard outputs 100 MHz and output signal 1400 MHz. The PLL Unit circuit is shown in Figure 4. Low noise receiver transmits the maser signal 1420 MHz to the low frequency 405.7 kHz. This is the operating frequency of the Phase Detector. Another signal comes to the Pha- se Detector from the Synthesizer which is able to change the output frequency within 1 x 10-10 range with the resolution of 1 x 10-15. Thus the Phase Detector controls the VCO frequency. Processor provides the possibility of monitoring different PLL Unit parameters and con- trols the standard output frequencies via RS-232 port. For more detail information see User’s Guide 411141.032 UG. Frequency divider produces 1PPS timing signals. Sync input enables output signals to be synchronized to external 1PPS signal. Figure 4 PLL Unit circuit Figure 3 Physics Package Layout