Multiprocessor Architecture Sample Clauses

Multiprocessor Architecture. 8 3.1.1 Homogeneous and Heterogeneous Systems . . . . . . . . . . . . . . . 8 3.1.2 Threading Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1.3 Symmetric Multiprocessing (SMP) . . . . . . . . . . . . . . . . . . . 10 3.2 Programming Model Design Decisions . . . . . . . . . . . . . . . . . . . . . . 14 3.2.1 The origins of different programming models . . . . . . . . . . . . . . 14 3.2.2 Describing parallelism with threads . . . . . . . . . . . . . . . . . . . 14 3.2.3 Choice of programming language . . . . . . . . . . . . . . . . . . . . 15 3.2.4 Machine-code generation . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.5 Memory model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.6 Parallel data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.7 Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.8 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.9 Library support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 Modifying Programs for Parallel Processing . . . . . . . . . . . . . . . . . . . 19 3.3.1 Algorithm Modifications . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.2 Data modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3.3 Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3.4 Automatic translation . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4 Current Programming Models . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4.1 Major GPU Programming Models . . . . . . . . . . . . . . . . . . . . 21 3.4.2 Other Major Programming Models . . . . . . . . . . . . . . . . . . . . 27 3.4.3 Other Programming Models . . . . . . . . . . . . . . . . . . . . . . . 29 3.5 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.5.1 Partitioning overheads . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.5.2 Processing performance . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.5.3 Memory performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.5.4 Automatic optimization . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.5.5 Coding time and efficiency . . . . . . . . . . . . . . . . . . . . . . . . 34 3.6 Portability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.6.1 Portability between classes of parallel processors . . . . . . . . . . . . 3...
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Multiprocessor Architecture. Since 1945, programming models for single processor systems have evolved with the assump- tion that the underlying hardware implements the Xxx Xxxxxxx architecture, a single thread executing instructions in program order. Improved semiconductor manufacturing and advanced microarchitectural techniques have increased performance by many orders of magnitude while presenting an essentially unchanged model to the programmer. More recently, the rate of increase has slowed, as both of these avenues of improvement have neared their limit. Therefore, other ways of improving computing performance are sought. An obvious way to improve performance is to use multiple discrete processors rather than just a single one. Major performance benefits can be realized this way, but as the number of parallel threads of execution (and thus performance) increases, the architectural model becomes more and more dissimilar to the Xxx Xxxxxxx model. Therefore, new programming models are needed to allow programmers to exploit the large number of threads becoming available. This chapter explores the various programming models which have sprung up to fill this gap. In order to understand the constraints these programming models are working with, a brief discussion of multiprocessor architectures is also included.
Sample 1

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