EXHIBIT 10.6
DESIGN AND PURCHASE CONTRACT
----------------------------
Dated April 11, 1997
Revised on May 12, 1997
Revised on June 4, 0000
Xxxxxxx
Xxxxxxx Electronics, Inc. 00 Xxxxxxxx Xx., Xxxxxx, Xxxxxx, X0X 0X0
(fax: 0-000-000-0000; E-mail: xxx@xxxxxxx.xxx)
(herein "Philsar")
And
Vectorlink, Inc. 00000 Xxxxxxx Xx., Xxxxxxx, Xxxxxxxxxx, 00000, XXX,
(fax: 0-000-000-0000; E-mail: xxx@xxxxxxxxxx.xxx)
(herein "Vectorlink")
1. Product
The item which is the subject of this agreement is the "VRF1" down converter
ASIC to be developed jointly by Vectorlink and Philsar, as more particularly
described in Schedule A (herein the "Product").
2. Background
The VRF1 is to be architected by Vectorlink with proprietary architecture to
work in concert with the Vectorlink 12 channel GPS digital signal processing
chip.
3. Scope of Design Work
Philsar will implement the architecture into a single down converter chip, using
Philsar proprietary RF technology, according to the specifications in Schedule
A and according to the timetable set out in Schedule B. Design work shall
include the production of 25 prototype copies of the Product.
4. Payment of Design Costs
Vectorlink will pay Philsar a portion of the NRE costs in respect of the
Product. The portion of NRE cost to be paid by Vectorlink is $70,000 USD which
shall be payable against Philsars' invoices in the amounts and according to the
timetable set out in Schedule C.
5. Post Contract Design Changes
Vectorlink may request modifications or alterations to the scope of the design
work at any time prior to the taping out of the design of the Product.
Vectorlink shall have 30 days fol-
Philsar - Vectorlink Design and Purchase Contract
Revised June 1997
page 1
CONFIDENTIAL TREATMENT REQUESTED. CONFIDENTIAL PORTIONS OF THIS DOCUMENT HAVE
BEEN REDACTED AND HAVE BEEN SEPARATELY FILED WITH THE COMMISSION.
lowing delivery of the prototype Product to request further design work. Philsar
shall not be obligated to accept any modification or alteration request nor
perform any additional design work, remedial or otherwise, unless and until a
mutually agreeable supplementary NRE budget has been established.
6. Intellectual Property
6.1. Vectorlink Ownership
Vectorlink retains ownership in the system architecture of the VRF1 chip, which
includes the following Vectorlink proprietary properties:
1- Frequency plan with unambiguous carrier phase down converting
2- Cascadable LO frequency to facilitate relative phase measurement,
3- Cascadable down converter chips to facilitate phase measurement at the
digital signal processing chip for purpose of attitude determination.
6.2. Philsar Ownership
Philsar shall retain ownership of the Mask Work Plots and other representations
of the chip topography of the Product. Nothing in this agreement shall confer
upon Vectorlink any right or license, express or implied, in respect of the
Product Mask Work Plots or chip topography.
6.3. Indemnity
Except in the case where the specifications in Schedule A were provided by
Vectorlink, Philsar shall indemnify Vectorlink with respect to any claim, action
or proceeding against Vectorlink alleging that the Product infringes any patent,
copyright, trademark or other intellectual property of a third party in Canada
or the United States. In addition to its obligation to indemnify, Philsar may,
at its option, (i) defend the action or proceeding, (ii) procure the right for
Vectorlink to use the Product, (iii) replace or modify the Product to be free of
the infringement claim, or (iv) require Vectorlink to return the Product and
refund the purchase price plus a reasonable allowance for use, damage and
obsolescence. This indemnity shall apply only if Vectorlink gives Philsar prompt
notice of the claim, action or proceeding, cooperates fully with Philsar in
its defence and settlement thereof and only to the extent that the claim, action
or proceeding relates specifically and directly to the Product. It shall not
apply merely because the Product was incorporated by Vectorlink into an item in
respect of which the action or proceeding was brought.
7. Production Purchase Commitments
7.1. Minimum Purchase Commitment
Vectorlink agrees to purchase and Philsar agrees to sell a minimum of 25,000
units of the Product during the Production Period. For the purposes of this
paragraph, "Production Period" means the 12 months next following the month in
which the prototypes are delivered
Philsar - Vectorlink Design and Purchase Contract
Revised June 1997
page 2
or any additional post delivery design work that is requested pursuant to
paragraph 4 is completed. If Vectorlink fails to take delivery of the full
25,000 units during the Production Period, Vectorlink shall pay Philsar, as
liquidated damages and not as penalty, the sum of US$250,000 less an allowance
equal to US$10.00 for each unit that Vectorlink does purchase during the
Production Period. If Vectorlink fails to Purchase more than 3,000 units in any
3 month period during the Production Period, then, Philsar may, after a 30
notice to remedy, deem that Vectorlink intends to purchase the balance of the
Production Period and invoice Vectorlink accordingly.
7.2. Price
The unit price for the production Product shall be calculated according to the
price quantity matrix set out in Schedule D. At any time after the 24th month
following delivery of the Prototype Philsar may change the price quantity matrix
in Schedule D upon 30 days notice to Vectorlink but Vectorlink may elect to
terminate rather than accept the new price.
7.3. Terms of Sale
Vectorlink shall provide Philsar with Purchase Orders specifying quantity and
delivery date with price as set out in Schedule D. All Purchase Orders shall be
delivered to Philsar not less than 30 days prior to the delivery date specified
therein. All Product shall be sold and delivered for factory and Vectorlink
shall assume title and risk at that point even if Philsar selects the shipper.
Payment of the purchase price is due 30 days after delivery. Vectorlink is
liable for all sales taxes, duties and like charges that may be imposed on the
sale or delivery of the goods and services to be provided by Philsar under this
agreement. Vectorlink shall pay interest at the rate of 1% per month on all
overdue mounts.
8. Exclusivity
Vectorlink shall have the exclusive right to purchase the Product for 24 months
after the receipt of first production delivery, unless the agreement is
terminated earlier.
The exclusivity is subject to Vectorlink notifying Philsar that it wishes to
proceed with production pursuant to paragraph 7.1.
After this 24 month period, Philsar may sell the chip to third parties. However,
Philsar agrees to give to Vectorlink a preference in terms of cost and delivery
schedule over eventual third party customers, according to an agreement to be
arrived at between both no later than 21 months after the first production
quantity order from Vectorlink.
Philsar may not licence the Vectorlink proprietary properties to any third party
without the prior approval from Vectorlink.
9. Announcement and Advertising
Vectorlink and Philsar will jointly announce the product at a mutually agreeable
time with mutually agreeable contents.
Philsar - Vectorlink Design and Purchase Contract
Revised June 1997
page 3
Following such announcement and taking the exclusivity to Vectorlink of item 8,
Philsar may advertise the existence of this agreement and of the resulting chip
in trade journals or other public media and shall give prior notice to
Vectorlink of any advertisement that names or otherwise identifies Vectorlink.
Following the initial announcement, Vectorlink may advertise the existence of
this agreement and of the resulting chip in trade journals or other public
media.
10. Warranties and Limitation of Liability
10.1. Design
Philsar shall design a chip that meets the specifications in Schedule A. Philsar
makes no representations or warranties that the Product shall be usable by
Vectorlink or at all. All NRE costs paid by Vectorlink during the design phase
shall be deemed to be earned by Philsar upon receipt by Vectorlink of Product
that meet the specifications of Schedule A. Philsar shall be able to rely upon
any drawings, test results or specifications provided by Vectorlink for
incorporation into the design of the Product. Vectorlink warrants that any
software provided by it to Philsar in connection with this agreement will be
free of viruses, worms or similar programs or instructions.
10.2. Production
Philsar will replace any items of the Product which do not meet the
specifications of Schedule A. Philsar's liability in respect of such defective
items shall be limited to replacement only and shall not extend to any direct,
indirect or consequential loss or damage resulting from the use of defective
items by Vectorlink or the customers of Vectorlink, whether or not such defects
are latent. Philsar shall be under no obligation to accept warranty claims from
Vectorlink's customers. The foregoing warranties ace exhaustive of Philsar's
warranties to Vectorlink and Vectorlink's customers and in lieu of any other
warranty express or implied including, without limitation, any warranty of
merchantability or fitness for purpose.
10.3. Prototype Testing
Within the context of this contract, Philsar will prepare a document describing
test procedures that will be performed on the prototypes, including functional
and performance tests. Philsar will be responsible to perform the functional
tests at its facility. Functional testing definition is included as schedule E
of this document.
Two evaluation boards will be provided by Philsar with provisions to interface
with Vectorlink's development receiver. The evaluation boards will have the
functionality of the brass boards delivered by Philsar, plus the added
functionality of dual AGC and power control.
Philsar - Vectorlink Design and Purchase Contract
Revised June 1997
page 4
11. Vectorlink use to Conform with Laws
Vectorlink represents and warrants to Philsar that the Product and any item into
which it may become incorporated by or on behalf of Vectorlink will not be used,
sold or delivered by Vectorlink in violation of the laws of Canada or the
jurisdiction in which Vectorlink is situate or to which it or its parent may be
subject. In the event that Philsar has reasonable grounds to believe that such
violation has occurred or is about to occur, Philsar may terminate the contract
and stop further shipments but such stoppage or termination shall not remove
Vectorlink's liability to pay for any Product already delivered.
12. Force Majeure
Philsar or Vectorlink shall be excused from failure to perform its obligations
under this agreement if such failure is due to events beyond its control. Such
events include, but are not limited to strikes, accidents, fires, wars,
government actions and interruptions in the delivery of parts, raw materials or
Product.
If such an event occurs, Philsar or Vectorlink may elect to terminate the
agreement, in which case the provisions of paragraph 11 shall apply, or suspend
it for a period of up to 30 days. The party terminating the agreement shall
promptly notify the other party of the occurrence of such an event and its
election. Vectorlink shall remain liable for timely payment for Product already
in transit.
13. Termination
Philsar may terminate this agreement if Vectorlink fails to pay any amount
payable by it hereunder or otherwise perform its obligations or an event of
force majeure occurs. In addition to any other remedies available to Philsar at
law or in equity upon termination, Vectorlink shall remain liable for all
Product already in transit and, except in the case of termination for force
majeure, for Philsar's reasonable expenses with respect to any work in progress
at the time of termination.
Vectorlink may terminate this agreement if Philsar fails to deliver according to
Schedule A, Schedule B or otherwise perform its obligation or an event of force
majeure occurs. Vectorlink's liability shall be limited in accordance with
Schedule B and Schedule C.
14. Notices
All notices shall be in writing and sent by fax or E-mail to the addresses set
out on page 1. All notices shall be deemed to have been received on the next
business day after they were sent.
15. Governing Law
This agreement shall be governed by the laws of Ontario, Canada without regard
to any
Philsar - Vectorlink Design and Purchase Contract
Revised June 1997
page 5
conflict of law principles and any proceedings to resolve disputes shall be
heard by the courts of Ontario.
16. Headings
The parties agree that the headings are for convenience only and do not form
part of this agreement.
17. Entire Agreement
Except for the Non-Disclosure Agreement between the parties dated April 7, 1997
and any purchase order delivered by Vectorlink, which are incorporated into this
agreement by reference, this agreement contains the entire agreement between
the parties.
Dated at Ottawa, Canada this 4th day of June 1997.
Philsar Electronics, Inc Vectorlink, Inc.
/s/ Xxx Xxxxxxx /s/ Xxxxxx X. Fan
----------------------------- -------------------------------------
per: Xxx Xxxxxxx, President per: Xxxxxx X. Fan, President 6/11/97
Philsar - Vectorlink Design and Purchase Contract
Revised June 1997
page 6
Schedule A
Product
Specifications
Philsar - Vectorlink Design and Purchase Contract
Revised June 1997
page 7
The VRF1 ASIC is an integrated ASIC front end dual conversion L-band RF receiver
developed for a Global Positioning System (GPS) Receiver application. The device
is packaged in a TQFP package and is designed to operate from a 3 volt supply.
The input is the L1 (1575.42 MHz) GPS signal. The output is a downconverted,
bandpass 2-bit quantized signal ready for digital signal processing.
The VRF1 contains a low noise amplifier (LNA), two frequency multipliers
(mixer), voltage controlled oscillator (VCO), fixed frequency dividers,
automatic gain control, crystal oscillator and proper filter and input matching
impedances.
FEATURES
. Fully Integrated GPS receiver
. Total Gain of over 120 dB
. Integrated LNA
. Supply voltage range + 2.7 to +3.7 V DC
. Low Profile TQFP Package
. Sign and Magnitude digital outputs
. Cascadable for multi-Rx fronts ends
. On chip PLL and oscillators
. C/A Code compatible
APPLICATIONS
GPS (Global Positioning System)
STRUCTURE
Bipolar Silicon Monolithic IC
ABSOLUTE MAXIMUM RATINGS
(Non Simultaneous)
Max Supply Voltage +5V
Max RF Input +15dBm
Max voltage on any pin tbd
Storage temperature -65C to +150C
Operating Junction Temperature tbd
10.2028 MHz Ref. Input 1.5 Vpp
Philsar - Vectorlink Design and Purchase Contract
Revised June 1997
page 8
Product Description
The block diagram of the VRF1 ASIC is shown in Figure 1 below. The VRF1 ASIC
consists of a number of functional blocks as described below.
LNA Options
External LNA
Internal LNA
1st RF Strip
External 2nd IF Filter
1st IF Strip
External 1st IF Filter
2nd IF Strip
AGC Control
Analog to Digital Converter
Phase Locked Loop Synthesizer
Loop Filter and Resonator
Reference Outputs
Crystal Oscillator Options
Power Down Capability
Power On Reset Function
Philsar - Vectorlink Design and Purchase Contract
Revised June 1997
page 9
(Image)
Figure 1 - Preliminary Block Diagram of the VRF1
Note: The pin-out may be modified up to the Critical Design Review
Philsar - Vectorlink Design and Purchase Contract
Revised June 1997
page 10
Electrical Characteristics
The Electrical Characteristics are guaranteed over the following operating
conditions
Temperature -40(Degrees)C to + 85(Degrees)C
Supply Voltage +2.7 to +3.7V
Test Conditions (Unless Otherwise stated):
Supply Voltage: +2.7 to +3.7V
Test Temperature: +25(Degrees)C
Table 1: Electrical Characteristics
----------------------------------------------------------------------------------------------------------------------------
CHARACTERISTIC SYMBOL MIN TYP MAX UNITS TEST CONDITIONS
============================================================================================================================
POWER SUPPLY
Normal Mode
DC current drain Icc 35 60 mA PD Set High
Stand-by Icc 1 mA PD set low
-----------------------------------------------------------------------------------------------------------------------------------
LNA1
Input Signal Frequency /f/in1 1575.42 MHz
Output Frequency (1st IF) /f/in1 1575.42 MHz
Noise Figure FLNA1 2.5 3.5 dB
Input Impedance Z\\inLNA1\\ 50 Omega VSWR = 2.0 max
Output Impedance Z\\0\\LNA1 50 Omega VSWR = 2.0 max
Output Third Order Intercept Point II3P\\LNA1in\\ -10 -2 dBm
Output 1dB Gain Comp Point P1\\LNA1in\\ -20 -12 dBm
Radiated LO Emission LOLNA1 -40 dBm Output Power at 1530MHz at
Gain GLNA1 12 18 dB Pin 30
-----------------------------------------------------------------------------------------------------------------------------------
1st RF STRIP
Input signal frequency /f/in 1400 1575.42 1750 MHz
Output Frequency (1st IF) f1 45.0 MHz LO1 = 1530.42 MHz
Conversion Gain G1 20 30 dB fin=1575.42MHz+/- 50MHz
Noise Figure F1 2.5 5 8 dB Zs = 50Omega
Input Impedance Z\\in\\ 50 Omega VSWR = 2.0
Differential Output Impedance Z\\0\\1 600 Omega VSWR = 2.0
RF Input Image Rejection IR1 20 30 dB\\c\\
Input 1dB Gain Compression P1\\in\\ -50 -40 dBm Referred to the input
Point
LO Radiated Emission LO1 dBm Output Power at 1530MHz at
-10 Pin 34
-----------------------------------------------------------------------------------------------------------------------------------
Philsar - Vectorlink Design and Purchase Contract
Revised June 1997
page 11
Table 1: Electrical Characteristics
--------------------------------------------------------------------------------------------------------------------------
CHARACTERISTIC SYMBOL MIN TYP MAX UNITS TEST CONDITIONS
==========================================================================================================================
1st IF STRIP
Input Frequency (1st IF) fl 45.0 MHz LO1 = 1530.42 MHz
Output Frequency (2nd IF) f2 6.014 MHz LO2 = 51.014 MHz
Conversion Gain G2 20 30 dB f1=45.0 MHz
Differential Input Impedance Z1\\in\\ 600 kOmega
Differential Output Impedance Z1\\out\\ 1 5 Omega
Input Compression Point P2 75 mVrms
IF Strip 3dB Bandwidth BW1 50 55 MHz
--------------------------------------------------------------------------------------------------------------------------
2nd IF STRIP
Input Frequency IF2 6.014 MHz
Output Frequency IF2 6.014 MHz
IF2 Output Amplitude VIF2 100 mV\\pp\\
IF2 1dB Bandwidth BW2 6.5 7 8 MHz
Maximum Gain G3 75 dB
Gain Control Range G\\AGC-R\\ 30 40 dB
AGC Time Constant /t/AGC 1 3 ms
Output Variation over 30dB Range G3B 1 2 dB
Input Control Voltage 0.5 2.5 V
2 BIT ADC
Sign Duty Cycle 50 %
Magnitude Duty Cycle 25 30 35% % at 100 mV\\pp\\
--------------------------------------------------------------------------------------------------------------------------
Philsar - Vectorlink Design and Purchase Contract
Revised June 1997
Page 12
Table 1: Electrical Characteristics
-----------------------------------------------------------------------------------------------------------------------------------
CHARACTERISTIC SYMBOL MIN TYP MAX UNITS TEST CONDITIONS
===================================================================================================================================
PLL SYNTHESIZER
LO1 Phase Noise P\\n\\ 1530.42 MHz
1 kHz - 68 - 65 dBc/Hz Note: Does not include
10 kHz - 75 - 70 dBc/Hz spurious signals
100 kHz - 00 - 00 xXx/Xx
0 XXx - 000 - 100 dBc/Hz
5 MHz - 120 - 100 dBc/Hz
10 MHz - 000 - 000 xXx/Xx
f\\LO\\ 1400 1530 1700 MHz
VCO Free Running Frequency P\\spur\\ - 50 dBc
VCO Spurious Note:
f\\ref\\
Reference Input T\\Iock\\ 00.0000 XXx xXX0x000xx\\xxx\\
XXX Lockup Time 5 10 msec
1530
REFERENCE OSCILLATOR f\\ref\\
Reference Oscillator Frequency 00.0000 XXx Xxxxxxxxxxx Mode Crystal
V\\refin\\ 70 mV\\rms\\ Note:
Input Reference Signal Xxxxx 000 Xxxxxxxx Xxxxxxxxx, XX coupled
Note:
Reference Output X\\xxxxxx\\ 00
Xxxxx 000 mV\\rms\\
Output Impedance 600 Omega
Output Non-Inverting relative
to Reference Oscillator Must drive 4 loads of input
Output Driving Capability impedence
-----------------------------------------------------------------------------------------------------------------------------------
Philsar - Vectorlink Design and Purchase Contract
Revised June 1997
Page 13
Table 1: Electrical Characteristics
-------------------------------------------------------------------------------------------------------------------------------
CHARACTERISTIC SYMBOL MIN TYP MAX UNITS TEST CONDITIONS
===============================================================================================================================
DIGITAL INTERFACES Note All Digital interfaces are
3V TTL levels unless otherwise
specified
2 BIT ADC
Sample Clock Input Frequency 7.6521 9 MHz Typically f\\CLK38\\/5
Sign Output 3V TTL 3V TTL Note:
Magnitude Xxxxxx 0 X XXX 0X XXX Note
Sample Clock to Sign/Mag Output t\\MAG\\ 20 ns
Sample Clock Level 3V TTL
AGC CONTROL(TBD)
POWER CONTROL
Power Down Time t\\PD\\ 3 mus Note: For Each of 3 Modes
Power Up Time t\\PU\\ 20 ms
CLOCK OUTPUTS
CLK10 f\\REF\\ 10.2028 MHz f\\REF\\
CLK38 f\\CLK38\\ 38.2605 MHz 3.75xf\\REF\\
CLK51 f\\CLK51\\ 51.014 MHz 5xf\\REF\\
Note: Clock Output are
100 mV rms / 600omega
-------------------------------------------------------------------------------------------------------------------------------
Philsar - Vectorlink Design and Purchase Contract
Revised June 1997
Page 14
Schedule B
Time Table
Philsar - Vectorlink Design and Purchase Contract
Revised June 1997
Page 15
The target delivery dates are shown in Table 2 below.
Table 2: Time Table
-------------------------------------------------------------------
Event Description Target Completion
Date
===================================================================
Contract Award December 23, 1996
-------------------------------------------------------------------
Detailed Specification Sheet January 10, 1997
-------------------------------------------------------------------
Preliminary Design Review February 5, 1997
-------------------------------------------------------------------
Critical Design Review May 15, 1997
-------------------------------------------------------------------
Tape Out June 30, 1997
-------------------------------------------------------------------
First Shipment of 25 Untested Part August 30, 1997
Accelerated Schedule (see Note 1 below)
-------------------------------------------------------------------
First Shipment of 25 Untested Part September 15, 1997
Normal Schedule
-------------------------------------------------------------------
Shipment of 2 Test Sets (see Note 3 below) September 30, 1997
-------------------------------------------------------------------
Shipment of 25,000 minimum First Purchase* 12 Weeks ARO
-------------------------------------------------------------------
Volume Production Orders 10 - 12 Weeks ARO
-------------------------------------------------------------------
* These target dates assume no second design cycle. Should such second
cycle be warranted, new target dates will be accepted by both parties.
Note 1
There may be an option to have a first shipment of parts using a special
ordering process to speed-up first delivery. This process will add $25,000
(twenty five thousand dollars) to the NRE cost of the project.
Note 2
These dates may vary by up to 30 days for unintended reasons. In such a
case, these target dates will be deemed as met for contractual purpose.
Note 3
These Test Sets will include:
- Test PCB Evaluation Board,
- Documentation Package including data sheets and a brief description
of the board set up and use requirements
- Successful Test Report including test data verifying all
specification items of the VRF1 GPSRx ASIC Specification in
Schedule A.
Philsar - Vectorlink Design and Purchase Contract
Revised June 1997
Page 16
Schedule C
Payment
Schedule
Philsar - Vectorlink Design and Purchase Contract
Revised June 1997
Page 17
The Schedule of Payments for the Project is shown in Table 3 below:
Table 3: Schedule of Payment
---------------------------------------------------------------------------------------------------------
Event Target Date Payment in
US Dollars
=========================================================================================================
Contract Award December 23, 1996 -
---------------------------------------------------------------------------------------------------------
Detailed Specifications January 10, 1997 [**]
---------------------------------------------------------------------------------------------------------
Preliminary Design Review February 5, 1997 [**]
---------------------------------------------------------------------------------------------------------
Critical Design Review May 15, 1997 [**]
---------------------------------------------------------------------------------------------------------
Tape Out to Production June 30, 1997 [**]
---------------------------------------------------------------------------------------------------------
Shipment of Prototypes - Normal Schedule September 15, 1997
---------------------------------------------------------------------------------------------------------
Shipment of Prototypes - Accelerated Schedule August 30, 1997
---------------------------------------------------------------------------------------------------------
Shipment of 2 Test Sets September 30, 1997 [**]
---------------------------------------------------------------------------------------------------------
Start of Shipment of 25,000 minimum First Purchase* November 1, 1997 [**]
---------------------------------------------------------------------------------------------------------
Total Contract Value [**]
or [**] for
accelerated
schedule
---------------------------------------------------------------------------------------------------------
* This target date assumes no second design cycle and a 12 week delay ARO.
Should such second cycle be warranted, new target dates will be accepted by
both parties. The payment schedule is to be consistent with item 7.3 of
this agreement.
Philsar - Vectorlink Design and Purchase Contract
Revised June 1997
Page 18
** CONFIDENTIAL MATERIAL REDACTED AND FILED SEPARATELY WITH THE COMMISSION.
Schedule D
Price/Quantity
Matrix
Philsar - Vectorlink Design and Purchase Contract
Revised June 1997
Page 19
The Unit Price of the parts will vary according to the cumulative number of
parts ordered, as shown in table 4 below:
Table 4: Price/Quantity Matrix
---------------------------------------------------------------
Quantity Unit Price in US dollars
===============================================================
Initial 25 Untested Prototypes included in design costs
---------------------------------------------------------------
Minimum Initial Purchase of [*] [*]
---------------------------------------------------------------
[*] [*]
---------------------------------------------------------------
[*] [*]
---------------------------------------------------------------
[*] [*]
---------------------------------------------------------------
[*] [*]
---------------------------------------------------------------
These prices are fixed for the period covering the first 24 months following
delivery of the functional prototypes.
Philsar - Vectorlink Design and Purchase Contract
Revised June 1997
Page 20
[*] CONFIDENTIAL MATERIAL REDACTED AND FILED SEPARATELY WITH THE COMMISSION.
Schedule E
Functionality
Tests
Philsar - Vectorlink Design and Purchase Contract
Revised June 1997
Page 21
Functionality Test Areas
After receiving the Prototypes from the Foundry, Philsar will perform, in its
facilities or under its direct supervision a series of tests to ensure the
functionality of the prototypes.
1. Temperature Ranges
The tests will be performed at 3 temperature ranges:
1.1. at -40 degrees Celsius
1.2. at +25 degrees Celsius
1.3. at +85 degrees Celsius
2. Test to be performed
The following components will be tested, each measuring a specific aspect of the
component for conformance to specifications of Table 5 below:
Table 5: Functional Test to be Performed by Philsar
------------------------------------------------------------------------------
No Component under test Aspects to be measured
==============================================================================
1 LNA Gain
Linearity
------------------------------------------------------------------------------
2 Mixer / LNA2 Conversion Gain
Linearity
Image Suppression
------------------------------------------------------------------------------
3 VCO Frequency Range
(On Spectrum Analyzer only) Phase Noise
------------------------------------------------------------------------------
4 Frequency Dividers Functionality
Output Clocks Divide Ratios
------------------------------------------------------------------------------
5 PLL Acquire Lock over Temperature Range
------------------------------------------------------------------------------
6 AGC Gain Range
Compression Ratio
Output Level
------------------------------------------------------------------------------
7 A/D Functionality, Magnitude / Sign, 30% duty
cycle at nominal level
Linearity
------------------------------------------------------------------------------
8 Crystal Oscillator Frequency, Power
------------------------------------------------------------------------------
9 Power Control 3 Functional Modes
------------------------------------------------------------------------------
A Report will be submitted to Vectorlink describing the results of the tests.
Philsar - Vectorlink Design and Purchase Contract
Revised June 1997
Page 22
