ANNEX 1 RDA TECHNOLOGIES LIMITED CORTEX-A7 MPCORE, CORTEX-A7 FPU, CORTEX-A7 NEON

Exhibit 4.15

ANNEX 1

RDA TECHNOLOGIES LIMITED

CORTEX-A7 MPCORE, CORTEX-A7 FPU, CORTEX-A7 NEON

TLA Number		LEC-TLA-00547
Legal Counsel		AF
Annex Effective Date		21 December 2012

This Annex, when signed by both parties, shall form part of and be incorporated into the Technology Licence Agreement (“TLA”) between the parties (document reference as identified in the table above). Solely for the purposes of interpretation of the TLA with respect to this Annex, to the extent that the provisions contained in this Annex conflict with any of the provisions of the TLA the provisions contained in this Annex shall prevail over and shall supersede the conflicting provisions in the TLA.

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SECTION 1 - ARM TECHNOLOGY

Key to Disclosure Rights

D		CONFIDENTIAL except disclosure permitted to “Designers” in accordance with Clause 3 of the TLA
M		CONFIDENTIAL except disclosure permitted to “Manufacturers” in accordance with Clause 3 of the TLA
T		CONFIDENTIAL except disclosure permitted to “Test Houses” in accordance with Clause 3 of the TLA
CS		CONFIDENTIAL except disclosure permitted to “Customers” in accordance with Clause 3 of the TLA
N		NON-CONFIDENTIAL

SECTION 1.1 — Cortex-A7 MPCore

CORTEX-A7 MP CORE

PART A TECHNICAL REFERENCE DOCUMENTS

Section 1

Technical Reference Manuals

Part Number		Description		Disclosure Rights		Delivery Date
***		Technical Reference Manual - PDF		N
***		Technical Reference Manual - FrameMaker		D
***		Errata List		N		Within ten working days of Annex Effective Date
***		CoreSight DAP Lite TRM - PDF		N
***		CoreSight DAP Lite TRM - FrameMaker		D
***		CoreSight DAP Lite Errata List - PDF		N

Section 2

Architecture Documentation

Part Number		Description		Disclosure Rights		Delivery Date
***		ARMv7-A -R Architecture Reference Manual		N
***		ARMv7-AR Debug Supporting Documentation		N		Within ten working days of Annex Effective Date
***		ARMv7-A -R Architecture Errata List		N
***		ARMv7-A -R Architecture Release Note		N

PART B IMPLEMENTATION & INTEGRATION DOCUMENTATION

Part Number		Description		Disclosure Rights		Delivery Date
***		Release Notes		D
***		Configuration and Signoff Guide		D
***		Integration Manual - PDF		D		Within ten working days of Annex Effective Date
***		Integration Manual - FrameMaker		D
***		CoreSight DAP Lite Release Note - PDF		D,CS
***		CoreSight Generic Components IG - PDF		D,CS

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PART C VERILOG MODELS

Section 1 Synthesizable RTL

Part Number		Description		Disclosure Rights		Delivery Date
***		Synthesizable Verilog RTL		D
***		Integration Synthesisable Verilog RTL		D
***		APB Access Port Verilog RTL		D		Within ten working days of Annex Effective Date
***		APBMUX for DAP Verilog RTL		D
***		Serial Wire JTAG dualmode Debug Port RTL		D
***		CoreSight DAP Lite Verilog RTL		D

Section 2 Implementation Scripts

Part Number		Description		Disclosure Rights		Delivery Date
***		Synopsys Reference Implementation Flow		D
***		Cadence Reference Implementation Flow		D
***		CoreSight DAP Lite Synthesis Scripts		D		Within ten working days of Annex Effective Date
***		CoreSight DAP Lite LEC Formality		D
***		CoreSight DAP Lite LEC Conformal		D

Section 3 IP-XACT Descriptions

Part Number		Description		Disclosure Rights		Delivery Date
***		IP-XACT Description		D		Within ten working days of Annex Effective Date

PART D RTL TEST BENCHES

Part Number		Description		Disclosure Rights		Delivery Date
***		Vector Capture and Replay Test Bench		D		Within ten working days of Annex Effective Date
***		RAM Integration Test Bench		D

N/A

PART E AVS

N/A

PART F FUNCTIONAL TEST VECTORS

Part Number		Description		Disclosure Rights		Delivery Date
***		CoreSight DAP Functional CRF		D,M,T,CS		Within ten working days of Annex Effective Date

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PART G FUNCTIONAL & INTEGRATION TEST

Part Number		Description		Disclosure Rights		Delivery Date
***		Portable Functional Test Source		D,M,T,CS
***		Portable Maximum Power Test Source		D,M,T,CS		Within ten working days of Annex Effective Date
***		Portable Power Indicative Test Source		D,M,T,CS
***		Integration Kit		D,M,T,CS

PART H MODELS

Part Number		Description		Disclosure Rights		Delivery Date
***		DSM Synopsys VCS Verilog Solaris		N
***		DSM Synopsys VCS Verilog Linux		N		Within ten working days of Annex Effective Date
***		DSM Synopsys VCS Verilog Solaris 64bit		N
***		DSM Synopsys VCS Verilog Linux AMD 64bit		N

PART I TECHNICAL NOTES

ISA is ARMv7A

Memory Architecture is Harvard

Pipeline length is 8 stages

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SECTION 1.2 — Cortex-A7 FPU

CORTEX-A7 FPU

PART A TECHNICAL REFERENCE DOCUMENTS

Section 1

Technical Reference Manuals

Part Number		Description		Disclosure Rights		Delivery Date
***		Technical Reference Manual - PDF		N
***		Technical Reference Manual - FrameMaker		D		Within ten working days of Annex Effective Date
***		Errata List		N

PART B IMPLEMENTATION & INTEGRATION DOCUMENTATION

Part Number		Description		Disclosure Rights		Delivery Date
***		Release Notes				Within ten working days of Annex Effective Date

PART C VERILOG MODELS

Section 1 Synthesizable RTL

Part Number		Description		Disclosure Rights		Delivery Date
***		Synthesizable Verilog RTL		D		Within ten working days of Annex Effective Date

PART D RTL TEST BENCHES

N/A

PART E AVS

N/A

PART F FUNCTIONAL TEST VECTORS

N/A

PART G FUNCTIONAL & INTEGRATION TEST

Part Number		Description		Disclosure Rights		Delivery Date
***		Portable Functional Test Source		D,M,T,CS		Within ten working days of Annex Effective Date

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SECTION 1.3 — Cortex-A7 NEON

CORTEX-A7 NEON

PART A TECHNICAL REFERENCE DOCUMENTS

Section 1

Technical Reference Manuals

Part Number		Description		Disclosure Rights		Delivery Date
***		Technical Reference Manual - PDF		N
***		Technical Reference Manual - FrameMaker		D		Within ten working days of Annex Effective Date
***		Errata List		N

PART B IMPLEMENTATION & INTEGRATION DOCUMENTATION

Part Number		Description		Disclosure Rights		Delivery Date
***		Release Notes		D		Within ten working days of Annex Effective Date

PART C VERILOG MODELS

Section 1 Synthesizable RTL

Part Number		Description		Disclosure Rights		Delivery Date
***		Synthesizable Verilog RTL		D		Within ten working days of Annex Effective Date

PART D RTL TEST BENCHES

N/A

PART E AVS

N/A

PART F FUNCTIONAL TEST VECTORS

N/A

PART G FUNCTIONAL & INTEGRATION TEST

Part Number		Description		Disclosure Rights		Delivery Date
***		Portable Functional Test Source		D,CS		Within ten working days of Annex Effective Date

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SECTION 2 - LICENCE AND SPECIAL CONDITIONS

A. Definitions

A.1 “Architecture” means the architecture identified in Section 1 Part I of this Annex 1.

A.2 “Architecture Documentation” means the architecture documentation identified in Section 1 Part A Section 2 of this Annex 1.

A.3 “ARM Compliant Core” means the Cortex-A7 MPCore subsystem as described and identified in the Technical Reference Manual and which;

(i) contains up to a maximum of four (4) integer CPUs, each of which;

(a) executes each and every instruction in the ARM Instruction Set;

(b) executes no additional instructions to those contained in the ARM Instruction Set;

(c) executes all instructions at an identical rate of cycles per instruction (“CPI”) to that specified in the Technical Reference Manual;

(d) exhibits the Architecture;

(e) exhibits the Pipeline Length; and

(f) is Single Issue;

(ii) implements the programmer’s model as identified in the Technical Reference Manual;

(iii) runs and passes the Functional Test Vectors;

(iv) implements the snoop control unit which controls data cache coherence in the manner described in the Technical Reference Manual; and

(v) has been verified in accordance with the provisions of Section 3 of this Annex 1.

A.4 “ARMv7A Instruction Set” means the ARMv7A application processor instruction sets as described in the Architecture Documentation.

A.5 “ARM Compliant Product” means any product designed by or for LICENSEE which has; (i) an ARM Compliant Core; and may in addition include (ii) either a Cortex-A7 FPU or Cortex-A7 Neon.

A.6 “ARM Instruction Set” means the instruction set identified in Section 1 Part I of this Annex 1.

A.7 “Cortex-A7 FPU” means the Cortex-A7 floating point unit as described and identified in the Technical Reference Manual with part number ***.

A.8 “Cortex-A7 NEON” means the media engine as described and identified in the Technical Reference Manualwith part number ***.

A.9 Intentionally left blank.

A.10 “End User Licence” means a license agreement substantially in the form set out in Section 10 of this Annex 1.

A.11 “Functional and Integration Test” means the relevant test files identified in Section 1 Parts G of this Annex 1.

A.12 “Functional Test Vectors” means the functional test vectors identified in Section 1 Part F of this Annex 1.

A.13 “Harvard Architecture” means a microprocessor architecture which dictates that the address and data memory system for instruction fetches and for data load/store operations are separate.

A.14 “Implementation and Integration Documentation” means the documentation identified in Section 1 Parts B of this Annex 1.

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A.15 “Implementation Scripts” means the deliverables identified in Section 1 Part C Section 2 of this Annex 1.

A.16 “IP-XACT Descriptions” means the deliverables identified in Section 1 Part C Section 3 of this Annex 1.

A.17 “Models” means; (i) the design simulation models identified in Section 1 Part H; and (ii) any other design simulation model for the Cortex-A7 MPCore which is generally available from ARM subject to; (a) receipt by ARM of a purchase order from LICENSEE requesting such design simulation model expressly subject to the terms and conditions of this Agreement; and (b) the payment by LICENSEE to ARM of the then current fee for such design simulation model as quoted by ARM from time to time.

A.18 “Pipeline Length” means the number of clocked stages through which each single-cycle instruction must pass to complete the execution of such instruction and identified in Section 1 Part I of this Annex 1.

A.19 “RTL Test Benches” means the program files identified in Section 1 Part D of this Annex 1.

A.20 “Single Issue” means that only one instruction is issued for execution within the integer unit in any single clock cycle, where for the purposes of this definition clock means the clock that advances the pipeline.

A.21 “Synthesizable RTL” means the deliverables identified in Section 1 Part C Section 1 of this Annex 1.

A.22 “Technical Reference Manual” means the relevant technical reference manuals identified in Section 1 Part A Section 1 of this Annex 1.

A.23 “Use” means in respect of the object code of the Models, the use of (including copying the object code of the Models to the extent that such copying is incidental to such use, including installation, backup and execution) the object code of the Models, or any part thereof. Use shall specifically exclude: (i) the translation, adaptation, arrangement or other alteration of the object code of the Models except as allowed by local legislation implementing Article 6 of the EC Directive on the legal protection of computer programs (91/250/EEC) and then only to the extent necessary to achieve interoperability of an independently created program with other programs; and (ii) the adapting or reverse compiling of the object code of the Models for the purpose of error correction.

B. Licence

B.1 Subject to the provisions of Clause 3 (Confidentiality) of the TLA and the provisions of this Section 2, ARM hereby grants, to LICENSEE, a non-transferable (subject to Clause 16.3 of the TLA), non-exclusive, world-wide licence for the Term to;

Technical Reference Manuals

(i) use, copy, modify (solely to the extent necessary to reflect any permitted modifications in accordance with the provisions of this Clause B.1 or for incorporation into LICENSEE’s documentation), distribute and have distributed the Technical Reference Manuals;

(ii) use and copy the Architecture Documentation for the purpose of designing and having designed (subject to the provisions of Clause 2.2 of the TLA) ARM Compliant Products;

ARM Compliant Core, Cortex-A7 FPU and Cortex-A7 NEON

(iii) use and copy the Implementation and Integration Documentation only for the purposes of designing and having designed (subject to the provisions of Clause 2.2 of the TLA) ARM Compliant Products;

(iv) use, copy and modify (solely for the purposes of scan insertion, buffer insertion, timing closure, targeting standard cell libraries, direct instantiations of cells for speed or power or area optimisation, use of licensee specified BIST and solely in relation to the Cortex-A7 MP Core changing any “Verilog Defines” which are stated as being modifiable in the Implementation and Integration Documentation and changing any configuration settings permitted in the relevant Implementation and Integration Documentation) the Synthesizable RTL, only for the purposes of designing and having designed (subject to the provisions of Clause 2.2 of the TLA) ARM Compliant Products;

(v) use, copy and modify the Implementation Scripts and IP-XACT Descriptions only for the purposes of designing and having designed (subject to the provisions of Clause 2.2 of the TLA) ARM Compliant Products;

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(vi) use, copy and modify the Functional and Integration Test only for the purposes of designing and having designed (subject to the provisions of Clauses 2.2 and 2.3 of the TLA) ARM Compliant Products;

(vii) use, copy and modify (solely for the purpose of and to the extent necessary to run the vectors on a simulator or tester) the Functional Test Vectors, only for the purposes of designing and having designed (subject to the provisions of Clauses 2.2 and 2.3 of the TLA), manufacturing and having manufactured (subject to the provisions of Clause 2.4 of the TLA), testing and having tested (subject to the provisions of Clause 2.5 of the TLA) ARM Compliant Products;

(viii) use, copy and modify the RTL Test Benches only for the purposes of designing and having designed (subject to the provisions of Clause 2.2 of the TLA) ARM Compliant Products;

(ix) manufacture and have manufactured (subject to the provisions of Clause 2.4 of the TLA) the ARM Compliant Products created under the licences granted in Clauses B.1(i) to B.1(viii) inclusive;

(x) test and have tested (subject to the provisions of Clause 2.5 of the TLA) the ARM Compliant Products manufactured under the licences granted in Clause B.1(ix);

(xi) package and have packaged (subject to the provisions of Clause 2.6 of the TLA), the ARM Compliant Products manufactured under the licences granted in Clause B.1(ix);

(xii) sell, supply and distribute encapsulated die of the ARM Compliant Products which have been manufactured and packaged under the licences granted in Clause B.1(ix) and B.1(xi);

Models

(xiii) copy and use, internally and for third party support purposes, the Models and related documentation;

(xiv) use, reproduce and distribute, and sub-license (subject to the terms of an End User Licence) the Use of the object code of the Models, solely for the purpose of developing ARM Compliant Products; and

(xv) modify, reproduce, use and distribute, in connection with the Models, the documentation related thereto.

C. Confidentiality

C.1 Notwithstanding the confidentiality provisions set out in Clause 3.5 of the TLA, LICENSEE may disclose any vectors created by or for LICENSEE and which have been derived from the Functional and Integration Test (“Derived Vectors”), to a Test House under a non-disclosure agreement containing substantially similar terms to Clause 3 of the TLA, except that the confidentiality period shall be, at a minimum, five (5) years from the date of disclosure to the Test House.

The Test House shall only be permitted to use the Derived Vectors for the purposes of testing ARM Compliant Products. The parties hereby agree that the foregoing shall be treated as a “have tested right” and accordingly the provisions of Clause 2.5 shall apply in respect of any disclosures of Derived Vectors to a Test House.

9

SECTION 3 - VERIFICATION

V.1 Definitions

V.1.1 “Implementation” means, in respect of the multiprocessor core, a unique physical layout for such multiprocessor core.

V.1.2 “RAM Integration Test Bench” means the test bench identified as part of the RTL Test Benches part number ***.

V.1.3 “Post Layout Synthesized Netlist” means a post layout synthesized netlist incorporating the ARM Compliant Core which; (i) obeys the Timing Constraints File in respect of such synthesis; and (ii) includes back annotated delays derived from the physical layout.

V.1.4 “Power-On Reset” means the reset mode of the ARM Compliant Core that is performed when power is first applied to the system.

V.1.5 “Timing Constraints File” means the timing constraints file determined by LICENSEE prior to final synthesis.

V.1.6 “Verification Confirmation” means the completed document in the form set out in Part C of Section 3 of this Annex 1.

V.2 Verification of ARM Compliant Core Implementation

V.2.1 For each Implementation of an ARM Compliant Core intended for incorporation in integrated circuits which will be distributed by or for LICENSEE, LICENSEE shall verify such Implementation by at least one of the following methods;

1. Verification by Equivalence Checking of RTL and Synthesized Netlist (See Part A)

2. LICENSEE Specified verification (See Part B)

Part A

Verification by Equivalence Checking of RTL and Synthesized Netlist

Methodology

Validation

V.A.1 Validate the Synthesisable RTL using the RAM Integration Test Bench in accordance with the Implementation and Integration Documentation and generate the validation log report (“Validation Logs”).

Verification

V.A.2 (i) use an equivalence checker to compare the Synthesisable RTL with the Post-Layout Synthesized Netlist and generate equivalence check log results (“RTL-Post Layout Equivalence Log Results”); (ii) run static timing analysis on the Post-Layout Synthesized Netlist and generate log results (“STA Log Results”); and (iii) simulate functional code on the Post-Layout Synthesized Netlist that will at least boot the ARM Compliant Core by performing a Power-On Reset and generate log results (“Post Layout Log Results”).

Delivery of Verification Confirmation

V.A.3 If the Validation Logs, RTL-Post Layout Equivalence Log Results, Post Layout Log Results and the STA Log Results (together the “Equivalence Log Results”) indicate that no errors have been detected (or the parties have

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jointly agreed a waiver in respect of any detected errors), LICENSEE shall deliver a Verification Confirmation to ARM and ARM shall acknowledge, in writing, the receipt by ARM of the Verification Confirmation within ten (10) working days of its receipt by ARM.

Verification Criteria

V.A.4 The Implementation of the ARM Compliant Core shall be verified when; (i) the Equivalence Log Results indicate that no errors have been detected (or the parties have jointly agreed a waiver in respect of any detected errors); and (ii) LICENSEE has received confirmation of receipt of the relevant Verification Confirmation from ARM in accordance with the provisions of Clause V.A.3.

Records and Delivery of Equivalence Log Results

V.A.5 For each ARM Compliant Product incorporating an Implementation of the ARM Compliant Core, LICENSEE shall keep a copy of the Equivalence Log Results for such ARM Compliant Product and shall deliver, as soon as reasonably possible, copies of such records to ARM upon request from ARM. If ARM reasonably concludes that the Implementation of the ARM Compliant Core has not been verified in accordance with the provisions of Clause V.A.4, then ARM shall indicate to LICENSEE the errors which ARM has detected and LICENSEE shall repeat the process prescribed in Clauses V.A.1- V.A.4.

Part B

LICENSEE Specified Verification

Methodology

V.B.1     Subject to V.B.4, use LICENSEE’s custom verification flow.

V.B.2 If LICENSEE elects such verification, LICENSEE shall, inform ARM in writing at least ninety (90) days prior to tape out of an ARM Compliant Product that LICENSEE wishes to use LICENSEE’s specified verification flow and supply to ARM a copy of the proposed verification flow (each a “Verification Flow”). Within 30 days of the receipt of the Verification Flow ARM shall notify LICENSEE in writing whether the Verification Flow has been accepted by ARM, which acceptance shall not be unreasonably withheld. If accepted by ARM, LICENSEE shall verify such ARM Compliant Products using the Verification Flow. If after acceptance of the Verification Flow by ARM, LICENSEE wishes to modify the Verification Flow LICENSEE shall submit the modified Verification Flow to ARM for re-acceptance prior to verifying the relevant Synthesisable ARM Compliant Core.

V.B.3 If ARM rejects either the Verification Flow or any modified Verification Flows, ARM shall provide LICENSEE with written reasons for such rejection together with any required changes. LICENSEE may resubmit the Verification Flow or any modified versions thereof to ARM for acceptance.

Default

V.B.4 If ARM fails to either accept or reject the Verification Flow within 30 days of ARM’s receipt of the Verification Flow from LICENSEE, then the relevant ARM Compliant Core shall be deemed verified.

Part C

Verification Confirmation

Verification in accordance with Section 3 Part A

1.    RAM Integration Test Bench

Description of process applied		Tool(s) used		Completed (Tick)
Running RAM Integration Test Bench

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2    Equivalence checking

Description of process applied		Tool(s) used		Completed (Tick)
ARM Compliant Core RTL to post-layout netlist *

* Process can be performed in one step or using several intermediate steps

3.    STA on Post-Layout Synthesized Netlist

Description of process applied		Tool(s) used		Completed (Tick)
Post-layout netlist

Verification in accordance with Section 3 Part B

Depending upon agreed verification methodology.

Partner

Partner Contact

Design name / number / ID

Process name

Library name

Core Name and Revision

Date

Signature

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SECTION 4 - SUPPORT LIMITATION

4.1 Except as provided below, the maximum number of man hours that ARM shall be obligated to expend on any individual support case submitted to ARM by LICENSEE shall be capped at sixteen (16).

4.2 If ARM reasonably believes that any individual support case will exceed the support cap referred to above, ARM and LICENSEE will mutually agree a plan of action for resolution of the support case.

4.3 If a support case results in a defect being identified, any time associated with correcting such defect will not be logged against such support case.

4.4 If ARM, at ARM’s discretion, determines that LICENSEE has entered multiple cases which relate to the same support problem, ARM shall be entitled to compile these into a single case which in aggregate will be subject to the cap referred to above.

4.5 If ARM agrees to provide support at LICENSEE’s premises in accordance with the provisions of Clause 7.3 of the TLA, any time spent at LICENSEE’s premises including travel shall not be included as part of the support cap.

SECTION 5 - TRAINING REQUIREMENT

Subject to the payment of the Training Fee (set out in Section 8 of this Annex 1), ARM shall make available the following training to LICENSEE

Training Course		Commencement Date		Course Length (Days)		Number of Permitted Trainees
3 day Cortex-A7MP hardware training course.		Within twelve (12) months of the Annex Effective Date		3		12

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SECTION 6 - TRADEMARKS

Trademark		Registered/ Unregistered
Part A
ARM w/bar [logo] Exhibit A		Registered
Part B
ARM Powered [logo] Exhibit B		Registered
Part C
ARM [logo] Exhibit C		Registered
Part D
ARM Connect Community Partner [logo] Exhibit D		Unregistered
Part E
ARM		Registered
Cortex-A7		Unregistered

SECTION 7 - TERM

Unless terminated earlier in accordance with the provisions of Clause 14 of the TLA, this Annex 1 shall continue in force for a period of four (4) years

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SECTION 8 - FEES AND ROYALTIES

FEES

		US$
Fee (Descriptor)		Due		Payable		Due Date (Invoice Date)
Licence Fee for Cortex-A7MP		***
				***		Annex Effective Date
				***		5 months after Annex Effective Date
Licence Fee for Cortex-A7 NEON		***
				***		Annex Effective Date
				***		5 months after Annex Effective Date
Licence Fee for Cortex-A7 FPU		***
				***		Annex Effective Date
				***		5 months Annex Effective Date
Training Fee		***		***		Annex Effective Date
		TOTAL		***

Support and Maintenance

		Support and Maintenance Fees (US$)
Product(s)		Year 1*		Year 2**
Cortex-A7MP Cortex-A7 FPU Cortex-A7 NEON		***		***

* In respect of the first year of the Term, the support and maintenance fees shall be due on the Annex Effective Date.

** In respect of the second year of the Term, subject to request from LICENSEE, the support and maintenance fees shall be due on the first anniversary of the Annex Effective Date.

ROYALTIES

Currency:		US Dollars
Currency Conversion:		ASP in any currency other than US$ shall be converted to ASP in US$ using the average local currency/US$ exchange rate over the Quarter as published by the US Federal Reserve [see ▇▇▇▇://▇▇▇.▇▇▇▇▇▇▇▇▇▇▇▇▇▇.▇▇▇/▇▇▇▇▇▇▇▇/▇▇/]
Due:		At the end of each Quarter

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Payable:		In accordance with the prov isions of Clause 6 of the TLA.
Invoice Address:		22/F Bank of China Tower, ▇ ▇▇▇▇▇▇ ▇▇▇▇, ▇▇▇▇ ▇▇▇▇

Calculation:

For each unit of ARM Compliant Product distributed by LICENSEE, LICENSEE shall pay a Royalty determined from the following table:

Cumulative Number of Units of ARM		Royalty Rate
Compliant Products		ARM Compliant						ARM Compliant
containing the ARM Compliant Core distributed by LICENSEE as encapsulated die		Product containing an ARM Compliant Core with one (1) integer CPU (“Base Royalty” Rate)		ARM Compliant Product containing an ARM Compliant Core with two (2) integer CPU’s		ARM Compliant Product containing an ARM Compliant Core with three (3) integer CPU’s		Product containing an ARM Compliant Core with four (4) integer CPU’s
0 — 5,000,000		The greater of ***% of ASP and $***		*** x Base Royalty Rate		*** x Base Royalty Rate		*** x Base Royalty Rate
5,000,001- 10,000,000		The greater of ***% of ASP and $***		*** x Base Royalty Rate		*** x Base Royalty Rate		*** x Base Royalty Rate
10,000,001 — 50,000,000		The greater of ***% of ASP and $***		*** x Base Royalty Rate		*** x Base Royalty Rate		*** x Base Royalty Rate
>50,000,000		The greater of ***% of ASP and $***		*** x Base Royalty Rate		*** x Base Royalty Rate		*** x Base Royalty Rate

The multipliers used in the above table apply to both the ASP dollar calculations and the minimum royalty amounts specified.

For the purpose of calculating Royalties, only the distribution by the entity exercising the licences to distribute die of ARM Compliant Products which have been manufactured under this Annex 1 (notwithstanding that such distribution may be between RDA and a Subsidiary of RDA or between Subsidiaries of RDA) shall be relevant.

All Royalties paid to ARM pursuant to this Annex 1 shall be non refundable.

In an ARM Compliant Product with more than one ARM core embedded into the same piece of silicon, the royalties for each core in the device shall be cumulated, starting with the cores that have the highest royalty. The total royalty payable on the second and subsequent cores in accordance shall be reduced in accordance with the following table;

Core		% of royalty payable
ARM core with highest royalty		***% of applicable Royalty
ARM core with same or second highest royalty		***% of applicable Royalty
ARM core with same or third highest royalty		***% of applicable Royalty
ARM core with same or fourth highest royalty		***% of applicable Royalty
each subsequent ARM core		***% of applicable Royalty

Notwithstanding anything to the contrary contained in any other Annex 1, where an ARM Compliant Product contains an ARM Compliant Core and any other ARM cores, the multiple core royalty table of the ARM core with the highest royalty shall apply.  If the ARM core with the highest royalty is the ARM Compliant Core, the multiple core royalty table set forth above shall apply.

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Note for the purposes of calculating royalties the ARM Compliant Core shall be counted as a single ARM core irrespective of whether there are one or two integer CPUs contained within the subsystem.

Example 1:

An ARM Compliant Product contains three Cortex-A7 MP Cores, each with 2 integer CPUs, the ASP of the ARM Compliant Product is US$*** and the royalty payable on the cumulative volume is ***% ASP subject to a floor of US$***.

Total Royalty = US$***(floor amount) + ($***x*** – for second core) + ($***x *** – for third core) = US$***

Example 2:

An ARM Compliant Product contains three Cortex-A7 MP cores, each with 2 integer CPUs, with an applicable royalty rate of ***% and two ARM968E-S cores with an applicable royalty rate of ***% subject to a floor of US$***.  The ASP of the ARM Compliant Product is US$***.

Total royalty = ($***x***% for Cortex-A7 MP core) + ($***x***%x*** – for second Cortex-A7 MP core) + ($***x***%x*** for third Cortex-A7 MP core) + ($***x*** –fourth core  (floor applies)) + ($***x*** – fifth core  (floor applies)) = US$***

ROYALTY REPORT

Form of Royalty Report

Send to: The address for ARM set out in the TLA via first class mail and to ▇▇▇▇▇▇▇▇▇▇▇▇▇▇@▇▇▇.▇▇▇ via email.

LICENSEE

LICENSEE contact

Quarter for which report relates to

Table 1

Part Number

Intended Application

Number of Units of ARM Compliant Product distributed by LICENSEE in Quarter

ASP (US$)

Applicable Royalty Rate

Royalty Due

$

XXX

X

%

$

XXX

$

XXX

X

%

$

XXX

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Table 2

Part Number

Intended Application

Estimated Number of Units of ARM Compliant Product distributed by LICENSEE in Next Calendar Quarter

ASP (US$)

Applicable Royalty Rate

Royalty Due

$

XXX

X

%

$

XXX

$

XXX

X

%

$

XXX

The information provided in Table 2 shall be non-binding, supplied in good faith and treated as LICENSEE’s Confidential Information.

SECTION 9 — MARKETING

Notwithstanding anything to the contrary contained in the TLA either party may disclose to third parties that LICENSEE is a licensee of the ARM Technology licensed under this Annex 1. Except as expressly provided in the TLA, no right is granted to either party to disclose the terms and conditions of the TLA or this Annex 1.

Within sixty days (60) days of the Annex Effective Date the parties shall mutually agree the terms and method of issuance of a written announcement, which may be a press release, relating to the technology licensed under this Annex 1 and the relationship of the parties.

All communications for the above marketing activities shall be sent to the following contacts:

ARM Marketing Contact		LICENSEE Marketing Contact
Director of Corporate Communications
▇▇▇▇▇▇▇▇▇▇▇▇▇@▇▇▇.▇▇▇
▇▇▇ ▇▇▇▇▇▇▇▇ ▇▇▇▇
Cambridge
CB1 9NJ

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SECTION 10 — END USER LICENCE

[Respective LICENSEE entity]  (“LICENSOR”) hereby grants and the LICENSEE hereby accepts a non transferable and non-exclusive licence to use the Model solely for the purpose of developing a product which incorporates a CPU manufactured under LICENSOR’s licence from ARM (“Purpose”), under the following terms and conditions:

1. Ownership.  The Model is the property of ARM LIMITED and/or its licensors. The LICENSEE acquires no title, right or interest in the Model other than the licence rights granted herein.

2. Use.  The LICENSEE may use the Model on any one computer at one time except that the Model may be executed from a common disc shared by multiple CPUs provided that one authorised copy of the  Model has been licensed from LICENSOR for each CPU concurrently executing the Model.

LICENSEE shall not reverse engineer, decompile or disassemble the Model, in whole or in part.

LICENSEE shall only be permitted to use the Model for the Purpose.

LICESENSOR hereby authorises LICENSEE to concurrently use up to a maximum number of [       ] copies of the Model

3. Copies.  Except as provided in Clause 2, LICENSEE may make copies of the Model for back-up and archival purposes only. All copies of the Model must bear the same notice(s) contained on the original copies supplied by LICENSOR.

4. Model Limited Warranty. LICENSOR warrants that the disks containing the Model shall be free from defects and workmanship under normal use and the programs will perform in accordance with the accompanying documentation for a period of ninety (90) days from the date of delivery.  Any written or oral information or advice given by LICENSOR distributors, agents or employees will in no way increase the scope of this warranty. LICENSOR’s entire liability and the LICENSEE’s exclusive remedy will be, at LICENSOR’s sole option, to replace the disk or to use LICENSOR’s reasonable efforts to make the Model meet the warranty set forth above.  Any replacement Model will be warranted for the remainder of the original warranty period or thirty (30) days, whichever is the longer. The LICENSEE agrees that the supply of the Model does not include updates and upgrades, which may be available from LICENSOR under a separate support agreement.

THE ABOVE WARRANTIES ARE EXCLUSIVE AND IN LIEU OF ALL OTHER WARRANTIES, WHETHER EXPRESS OR IMPLIED INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.

IN NO EVENT SHALL LICENSOR BE LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES RESULTING FROM ITS PERFORMANCE OR FAILURE TO PERFORM UNDER THIS AGREEMENT OR THE FURNISHING, PERFORMANCE, OR USE OF ANY MODEL LICENSED HERETO, WHETHER DUE TO BREACH OF CONTRACT, BREACH OF WARRANTY, OR NEGLIGENCE EVEN IF LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

THE MAXIMUM LIABILITY OF LICENSOR SHALL BE LIMITED TO REFUND OF THE FEES PAID BY LICENSEE (IF ANY) FOR THE MODEL.

5. Assignment of the Agreement.  This Agreement and any license granted hereunder to the LICENSEE may not be assigned, sub-licensed or otherwise transferred by the LICENSEE to any third party

6. Term and Termination.  Unless terminated in accordance with the provisions of this Clause 6, this Agreement and licenses granted hereunder shall continue in force until completion of the Purpose.  LICENSOR may terminate this Agreement by written notice to the LICENSEE in the event  of a breach by  LICENSEE of any provisions of this Agreement.

Upon expiration or termination of this Agreement, the LICENSEE shall refrain from any further use of the Model, and LICENSEE shall either return or destroy and copies of the Model in it’s possession at the date of expiration of termination as applicable.

7. Applicability.  The limitations and exclusions above may not apply in certain countries or states where they conflict with local law. In cases where such a conflict exists the local law shall prevail and the remaining provisions of the Agreement shall remain in full force and effect.

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IN WITNESS WHEREOF the parties have caused this Annex 1 to be signed by their duly authorised representative:

ARM LIMITED			RDA TECHNOLOGIES, LIMITED.
BY:	/s/ ▇▇▇▇ ▇▇▇▇▇▇		BY:	/s/ ▇▇▇▇▇▇▇ ▇▇▇
NAME:	▇▇▇▇ ▇▇▇▇▇▇		NAME:	▇▇▇▇▇▇▇ ▇▇▇
TITLE:	Chief Commercial Officer		TITLE:	CEO
DATE:	8-1-13		DATE:	2012.12.19

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