Test Pattern Sample Clauses

Test Pattern. DocMemory’s memory test patterns are carefully designed and used to detect specific problems on a memory module. It has several kinds of test patterns that the industry recognizes as excellent choices for uncovering assembly errors and memory cells failures.The following list shows an example of Test pattern selections available in the software. Fig 4.2.2• Walk Data "0" & "1"This pattern is designed to find Open/Short data lines. The walking "1" test writes a data pattern into some arbitrary locations and reads back the information to see whether the data pattern is unchanged. It works the same way for the walking "0" pattern except the data pattern is now inverted. • Walk Address "0" & "1"This pattern is designed to detect address lines that are short, open, stuck or are having missing bits error. For Walking "1", DocMemory first choose all those locations that can test single address lines and fill these locations with an arbitrary data pattern. Each single location is rewritten with its complimentary pattern.(eg. 0x55 => 0xaa ). If any change is detected, it can be concluded that there are problems on the address line. The same process is repeated with Walking "0" except the address locations are now inverted. • MATS+March Test is a well defined test pattern designed to uncover memory cell failures such as address decoder faults, stuck at faults and cell interaction problems. • March BMarch B is similar to other March Test algorithm except it uses a much more detailed testing method. It is designed to unveil various faults like : AFs (Address decoder Faults), SAFs (Stuck At Faults), TFs (Transition Faults), CFins ( Coupling Inversion Faults) linked with TFs or CFids, and CFids ( Coupling Idempotent Faults) linked with TFs or CFids. • March C-March C- is implement to detect AFs (Address decoder Faults), SAFs (Stuck At Fault), TFs (Transition Faults) unlinked CFins ( Coupling Inversion Faults), unlinked CFids ( Coupling Idempotent Faults) and CFsts ( State Coupling Faults). • CheckerboardThe test is designed to exercise each individual cell in the memory module to find possible shorts between adjacent columns and data buses. It writes a certain pattern to all even column and its complimentary pattern to all the odd column cells. It then reads back the data from each column and row to verify whether it is correct. • BurstThis test is designed to check for burst functionality in a read or write cycle.

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